| 2008 | ISCAS | A 0.18-m CMOS clock and data recovery circuit with reference-less dual loops. | Miao Li, Tad A. Kwasniewski, Shoujun Wang |
| 2007 | ISCAS | A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. | Muhammad Usama, Tad A. Kwasniewski |
| 2006 | DAC | PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. | William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel |
| 2006 | ISCAS | A 0.18m CMOS clock and data recovery circuit with extended operation range. | Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang |
| 2006 | ISCAS | An eye detection technique for clock and data recovery applications. | Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski |
| 2005 | ASPDAC | A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18m CMOS technology. | Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao |
| 2005 | ISCAS | An all-digital data recovery circuit optimization using Matlab/Simulink. | S. I. Ahmed, Tad A. Kwasniewski |
| 2005 | ISCAS | Decision feedback equalization for high-speed backplane data communications. | Jing Chen, Miao Li, Tad A. Kwasniewski |
| 2005 | ISCAS | A 0.18m CMOS transceiver design for high-speed backplane data communications. | Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang |
| 2004 | ISCAS | 2.4 GHz RF down-conversion mixers in standard CMOS technology. | Arif A. Siddiqi, Tad A. Kwasniewski |
| 2004 | ISCAS | Design and comparison of CMOS Current Mode Logic latches. | Muhammad Usama, Tad A. Kwasniewski |
| 1999 | ISCAS | A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. | Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski |
| 1999 | ISCAS | Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. | Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim |
| 1996 | VTS | Is High Frequency Analog DFT Possible? | Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jrme Wojcik |
| 1994 | VTC | A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems. | D. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc |