| 2014 | ICSEng | Rule Induction Based on Logic Synthesis Methods. | Grzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba |
| 2011 | ICSEng | Reduction of Knowledge Representation Using Logic Minimization Techniques. | Grzegorz Borowik, Tadeusz Luba, Dawid Zydek |
| 2009 | DDECS | Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. | Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski |
| 2008 | ISCAS | Logic synthesis method for FPGAs with embedded memory blocks. | Mariusz Rawski, Tadeusz Luba, Bogdan J. Falkowski |
| 2007 | DDECS | Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs. | Grzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba |
| 2005 | DSD | Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. | Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba |
| 2003 | DSD | NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. | Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba |
| 2003 | DSD | An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. | Mariusz Rawski, Henry Selvaraj, Tadeusz Luba |
| 1998 | VLSID | Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. | Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba |
| 1995 | DATE | A balanced multilevel decomposition method. | Henry Selvaraj, Tadeusz Luba |