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Taiga Takata

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

5

Venues

4

Active years

2006–2011

Best venue rank

C

Where they publish

Papers

5 indexed papers, newest first.

YearVenueTitleAuthors
2011IOLTSA robust algorithm for pessimistic analysis of logic masking effects in combinational circuits.Taiga Takata, Yusuke Matsunaga
2011IOLTSMultiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010FPGAA heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).Taiga Takata, Yusuke Matsunaga
2008ASPDACArea recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs.Taiga Takata, Yusuke Matsunaga
2006ISCASA character size optimization technique for throughput enhancement of character projection lithography.Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura