Tanay Karnik
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
26
Venues
9
Active years
1995–2025
Best venue rank
A*
Where they publish
Papers
26 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ICCAD | Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration. | Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik |
| 2023 | ICIP | CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder. | Prerna Budhkar, Navneet Rao, Jainaveen Sundaram, Tanay Karnik |
| 2022 | ISCAS | Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. | Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan |
| 2021 | DATE | A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. | Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Dileep Kurian, Indranil Chakraborty, Sirisha Rani Kale, Nilesh Jain, Tanay Karnik, Ravi R. Iyer, Anuradha Srinivasan |
| 2018 | DAC | Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. | Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang |
| 2018 | ISCA | Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. | Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang |
| 2014 | ASPDAC | Resiliency for many-core system on a chip. | Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar |
| 2013 | DAC | Power management and delivery for high-performance microprocessors. | Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar |
| 2012 | DATE | Design for test and reliability in ultimate CMOS. | Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky |
| 2012 | ICCAD | Scaling the "Memory Wall": Designer track. | Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held |
| 2010 | ASPDAC | Resilient design in scaled CMOS for energy efficiency. | James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De |
| 2010 | ISLPED | Resilient microprocessor design for high performance & energy efficiency. | Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De |
| 2009 | DAC | Circuit techniques for dynamic variation tolerance. | Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar |
| 2009 | ICCAD | Resilient circuits - Enabling energy-efficient performance and reliability. | James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik |
| 2006 | ISCAS | High-frequency DC-DC conversion : fact or fiction. | Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner |
| 2006 | ISLPED | Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. | Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik |
| 2006 | ISLPED | Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. | Hao Yu, Yiyu Shi, Lei He, Tanay Karnik |
| 2006 | VLSID | Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. | Ruchir Puri, Tanay Karnik, Rajiv V. Joshi |
| 2005 | DAC | Logic soft errors in sub-65nm technologies design and CAD challenges. | Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang |
| 2004 | DAC | Design and reliability challenges in nanometer technologies. | Shekhar Borkar, Tanay Karnik, Vivek De |
| 2004 | ICCAD | HiSIM: hierarchical interconnect-centric circuit simulator. | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
| 2004 | ISLPED | Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De |
| 2003 | DAC | Parameter variations and impact on circuits and microarchitecture. | Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De |
| 2002 | DAC | Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. | Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar |
| 2002 | ICCAD | Sub-90nm technologies: challenges and opportunities for CAD. | Tanay Karnik, Shekhar Borkar, Vivek De |
| 1995 | ICCAD | An empirical model for accurate estimation of routing delay in FPGAs. | Tanay Karnik, Sung-Mo Kang |