| 2010 | ASPDAC | Scan-based attack against elliptic curve cryptosystems. | Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | State-dependent changeable scan architecture against scan-based side channel attacks. | Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2010 | ISCAS | Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. | Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ASPDAC | Exact and fast L1 cache simulation for embedded systems. | Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | ITC | Design-for-secure-test for crypto cores. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | GECOM: Test data compression combined with all unknown response masking. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2008 | ASPDAC | Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 | Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2007 | ISCAS | Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. | Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2006 | ASPDAC | FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. | Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | ASPDAC | A processor core synthesis system in IP-based SoC design. | Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | ISCAS | Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. | Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A cosynthesis algorithm for application specific processors with heterogeneous datapaths. | Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | Instruction set and functional unit synthesis for SIMD processor cores. | Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2004 | ASPDAC | A thread partitioning algorithm in low power high-level synthesis. | Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2003 | ASPDAC | A hardware/software partitioning algorithm for SIMD processor cores. | Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2002 | VLSID | VLSI Architecture for a Flexible Motion Estimation with Parameters. | Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2001 | ASPDAC | Area/delay estimation for digital signal processor cores. | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2000 | ASPDAC | An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). | Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1999 | ASPDAC | A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. | Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. | Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1998 | ASPDAC | An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. | Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki |
| 1997 | ASPDAC | A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1995 | ASPDAC | Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1994 | ICCAD | A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1994 | ISCAS | A Simultaneous Placement and Global Routing Algorithm for FPGAs. | Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki |
| 1992 | ICCAD | An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. | Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki |
| 1990 | DAC | A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. | Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki |
| 1979 | COMPSAC | One-dimensional logic gate assignment and interval graphs. | Tatsuo Ohtsuki, Hajimu Mori, Ernest S. Kuh, Toshinobu Kashiwabara, Toshio Fujisawa |