| 2018 | EWSN | Poster: Smart Self-Adaptive Clustering Technique for Collaborative Sensing in IoT Risk Contexts. | Jaime Zornoza, Gabriel Mujica, Jorge Portilla, Teresa Riesgo |
| 2018 | ISCAS | Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs. | Rodrigo Marino, Jos Manuel Lanza-Gutirrez, Teresa Riesgo, Miguel Holgado |
| 2015 | ISCAS | A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems. | Gabriel Mujica, Alejandro Garcia, Javier Gordillo, Jorge Portilla, Teresa Riesgo |
| 2015 | ISCAS | Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. | Alfonso Rodrguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2014 | FPL | A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. | Juan Valverde, Alfonso Rodrguez, Julio Camarero, Andrs Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2013 | FPL | A self-adaptive image processing application based on evolvable and scalable hardware. | Angel Gallego, Javier Mora, Andrs Otero, Blanca Lpez, Eduardo de la Torre, Teresa Riesgo |
| 2013 | IECON | A 3D multi-objective optimization planning algorithm for wireless sensor networks. | Danping He, Jorge Portilla, Teresa Riesgo |
| 2013 | IECON | On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs. | Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo |
| 2012 | FPL | Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. | Rubn Salvador, Andrs Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Luks Sekanina |
| 2012 | IECON | Simulation tool and case study for planning wireless sensor network. | Danping He, Gabriel Mujica, Jorge Portilla, Teresa Riesgo |
| 2012 | IECON | Hardware-software integration platform for a WSN testbed based on cookies nodes. | Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo |
| 2012 | IECON | Smart parking service based on Wireless Sensor Networks. | Jihoon Yang, Jorge Portilla, Teresa Riesgo |
| 2011 | FPL | Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastin Lpez, Gustavo M. Callic, Roberto Sarmiento |
| 2010 | DSD | A Modular Peripheral to Support Self-Reconfiguration in SoCs. | Andrs Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
| 2010 | DSD | High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. | Rubn Salvador, Flix Moreno, Teresa Riesgo, Luks Sekanina |
| 2010 | FPL | Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. | Andrs Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva |
| 2007 | ISCAS | Efficient Power Macromodeling Technique for IP-Based Digital System. | Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo |
| 2007 | ISCAS | Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. | Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo |
| 2006 | FPL | Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. | Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly |
| 2006 | ICINCO | Power estimation for register transfer level by genetic algorithm. | Yaseer Arafat Durrani, Teresa Riesgo, Felipe Machado |
| 2005 | RSP | Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. | Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo |
| 2004 | FPL | Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. | Mario Garca-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo |
| 2000 | RSP | Highly Configurable Control Boards: A Tool and a Design Experience. | Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi |
| 1998 | DATE | Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. | Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda |