| 2025 | ASPDAC | Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes. | Sota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka |
| 2025 | ASPDAC | Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection. | Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka |
| 2025 | ISCAS | A 172.1dB-FoM 19.5kHz-BW DT ΔΣ ADC Using CLS-Assisted Fast Self-Quenching Floating Inverter Amplifier with Sampling Noise Cancellation. | Ximing Wang, Yo Kumano, Tomohiro Nezuka, Yoshikazu Furuta, Tetsuya Iizuka |
| 2024 | ISCAS | A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. | Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham |
| 2022 | ISCAS | A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. | Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka |
| 2017 | ASPDAC | CMOS-on-quartz pulse generator for low power applications. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2017 | ASPDAC | A 15 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2017 | ETS | Extension of power supply impedance emulation method on ATE for multiple power domain. | Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2016 | DATE | Analytical design optimization of sub-ranging ADC based on stochastic comparator. | Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2016 | ITC | Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. | Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2015 | DDECS | An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2013 | ASPDAC | High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. | Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada |
| 2011 | ASPDAC | All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. | Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2011 | DDECS | An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. | Tetsuya Iizuka, Kunihiro Asada |
| 2010 | DDECS | Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. | Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2006 | DATE | Timing-driven cell layout de-compaction for yield optimization by critical area minimization. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 2006 | ISCAS | Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 2004 | ASPDAC | High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
| 1998 | PAKDD | Automatic Visualization Method for Visual Data Mining. | Yuichi Iizuka, Hisako Shiohara, Tetsuya Iizuka, Seiji Isobe |
| 1988 | ICCD | Large memory embedded ASICs. | Tetsuya Iizuka, Takayasu Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi |