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Thomas Roewer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

3

Venues

2

Active years

2012–2018

Best venue rank

A*

Where they publish

Papers

3 indexed papers, newest first.

YearVenueTitleAuthors
2018MICROApplication-Transparent Near-Memory Processing Architecture with Memory Channel Network.Mohammad Alian, Seungwon Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam J. McPadden, Oliver O'Halloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-Mei W. Hwu, Nam Sung Kim
2017MICROContutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim, Adam J. McPadden, Daniel M. Dreps, Dean Sanner, Jan van Lunteren, Sameh W. Asaad
2012FPGAA cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, Jos A. Tierno