Tohru Sasaki
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
1980–2017
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | SMC | Development of a hug request motion model during active approach to human. | Mitsuru Jindai, Shunsuke Ota, Toshiyuki Yasuda, Tohru Sasaki, Yoshihiro Sejima |
| 1986 | DAC | HAL II: a mixed level hardware logic simulation system. | Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike |
| 1984 | ITC | Logic Design Verification Using Automated Test Generation. | Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka |
| 1983 | DAC | HAL: A block level HArdware Logic simulator. | Tohru Sasaki, Nobuhiko Koike, Kenji Ohmori, Kyoji Tomita |
| 1983 | ITC | A High Level Test Pattern Generation Algorithm. | Masato Kawai, Hideo Shibano, Shigehiro Funatsu, Shunichi Kato, T. Kurobe, K. Ookawa, Tohru Sasaki |
| 1981 | DAC | Hierarchical design verification for large digital systems. | Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato |
| 1980 | DAC | MIXS: A mixed level simulator for large digital system logic verification. | Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu |