| 2013 | DSD | Industrial Application of IEEE P1687 for an Automotive Product. | Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath |
| 2010 | ITC | Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. | Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab |
| 2005 | ITC | Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain. | Tom Waayers, Richard Morren, Roberto Grandi |
| 2004 | ITC | Extending the Digital Core-based Test Methodology to Support Mixed-Signal. | Geert Seuren, Tom Waayers |
| 2003 | ITC | An extension to JTAG for at-speed debug on a system. | Leon van de Logt, Frank van der Heyden, Tom Waayers |
| 2003 | ITC | An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. | Tom Waayers |
| 2002 | ITC | EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
| 2002 | ITC | Core-Based Scan Architecture for Silicon Debug. | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
| 2001 | ITC | Enhanced reduced pin-count test for full-scan design. | Harald P. E. Vranken, Tom Waayers, Hrv Fleury, David Lelouvier |