| 2015 | ETS | A practical approach for logic simplification based on fault acceptability for error tolerant application. | Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue |
| 2015 | ETS | Designing area-efficient controllers for multi-cycle transient fault tolerant systems. | Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue |
| 2015 | ICCD | Logic simplification by minterm complement for error tolerant application. | Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue |
| 2014 | ICCD | Compact and accurate stochastic circuits with shared random number sources. | Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue |
| 2012 | ICCD | Modeling economics of LSI design and manufacturing for test design selection. | Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue |
| 2011 | DDECS | Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. | Tsuyoshi Iwagaki, Kewal K. Saluja |
| 2008 | ICCD | Safe clocking register assignment in datapath synthesis. | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
| 2007 | ICCAD | Efficient path delay test generation based on stuck-at test generation using checker circuitry. | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
| 2005 | ETS | Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2004 | ETS | A design methodology to realize delay testable controllers using state transition information. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |