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Vikas Rana

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

23

Venues

5

Active years

2012–2026

Best venue rank

C

Where they publish

Papers

23 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCASVariability Aware Design of Memristor-based Gene Implementation in Cellular Neural Networks.Ahmed Magdy Abdelsamad, Vasileios G. Ntinas, Dimitrios A. Prousalis, Ioannis Messaris, Ahmet Samil Demirkol, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff
2026ISCASNovel M-CNN design fostering gradual switching of InGaZnO(IGZO)-based memristive devices.Peijia Yuan, Kristoffer Schnieders, Yongmin Wang, Vasilis Ntinas, Maria Elias Pereira, Vikas Rana, Alon Ascoli, Ronald Tetzlaff, Regina Dittmann, Stephan Menzel
2025ETSDependable Neuromorphic Computing-in-Memory Architectures.Farhad Merchant, Ankit Bende, Markus Fritscher, Shahar Kvatinsky, Simranjeet Singh, Vikas Rana, Regina Dittmann, Keerthi Dorai Swamy Reddy, Christian Wenger, Fouwad Jamil Mir, Mottaqiallah Taouil, Manil Dev Gomony, Said Hamdioui, Henk Corporaal
2025ISCASMemristor Resistance State Tuning with High-Frequency Periodic Inputs.Ioannis Messaris, Vasileios G. Ntinas, Dimitrios A. Prousalis, Ahmet Samil Demirkol, Ronald Tetzlaff, S. Zhang, Vikas Rana, Stephan Menzel, Alon Ascoli
2025ISCASLive Demonstration: 4 4 Memristive Cellular Nonlinear Network in EDGE detection operation.Yongmin Wang, Kristoffer Schnieders, Siyuan Jia, Vasileios G. Ntinas, Gennadiy Gvozdev, Felix Cppers, Susanne Hoffmann-Eifert, Alon Ascoli, Ronald Tetzlaff, Stefan Wiefels, Vikas Rana, Stephan Menzel
2024ASPDACMemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2024ETSError Detection and Correction Codes for Safe In-Memory Computations.Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
2024VLSIDExperimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
2024VLSIDHarnessing Entropy: RRAM Crossbar-based Unified PUF and RNG.Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay
2023ISCASDesign and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells.Vasileios G. Ntinas, Yongmin Wang, Ahmet Samil Demirkol, Ioannis Messaris, Vikas Rana, Stephan Menzel, Alon Ascoli, Ronald Tetzlaff
2022DATENEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Mller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cppers, Abdur R. Jalil, Qi Shu, Peter Schffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krger, Letcia Maria Bolzani Phls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grtzmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser
2022DATENeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.Felix Staudigl, Hazem Al Indari, Daniel Schn, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2022ISCASExperimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.Christopher Bengel, Stefan Wiefels, Vikas Rana, Hsin-Yu Chen, Qing-Tai Zhao, Rainer Waser, Henriette Padberg, Fengben Xi, Stephan Menzel
2022ISCASPerformance Analysis of Memristive-CNN based on a VCM Device Model.Yongmin Wang, Alon Ascoli, Ronald Tetzlaff, Vikas Rana, Stephan Menzel
2021ISCASImplementation of Multinary Łukasiewicz Logic Using Memristive Devices.Christopher Bengel, Anne Siemon, Vikas Rana, Stephan Menzel
2021ISCASTuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power.Wonjoo Kim, Dirk J. Wouters, Rainer Waser, Vikas Rana
2021VLSIDNegative Voltage Generator and Current DAC Based Regulator For Flash Memory.Vivek Tyagi, Shivam Kalla, Vikas Rana
2021VLSIDAdaptive Forward Body Bias Voltage Generator.Vivek Tyagi, Vikas Rana
2020VLSIDPower Efficient Sense Amplifier For Emerging Non Volatile Memories.Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti
2019VLSIDCurrent DAC Based -40dB PSRR Configurable Output LDO in BCD Technology.Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti
2018VLSIDCMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation.Vikas Rana
2016VLSID-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI.Amit Chhabra, Vikas Rana
2012ISCASRecent progress in redox-based resistive switching.Rainer Waser, Stephan Menzel, Vikas Rana