| 2010 | ITC | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2008 | ITC | Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. | Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar |
| 2007 | ASPDAC | AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar |
| 2007 | ICCAD | Variation-aware performance verification using at-speed structural test and statistical timing. | Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah |
| 2007 | VTS | An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. | Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland |
| 2006 | DAC | A flexible and scalable methodology for GHz-speed structural test. | Vikram Iyengar, Gary Grise, Mark Taylor |
| 2006 | DATE | Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. | Chunsheng Liu, Vikram Iyengar |
| 2006 | ITC | At-Speed Structural Test For High-Performance ASICs. | Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich |
| 2006 | VTS | Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. | Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan |
| 2005 | IROS | User interfaces for continuum robot arms. | Matthew A. Csencsits, Bryan A. Jones, William McMahan, Vikram Iyengar, Ian D. Walker |
| 2005 | VTS | Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. | Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, rika F. Cota |
| 2003 | DAC | Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. | Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty |
| 2003 | DATE | A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. | Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty |
| 2003 | VTS | Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar |
| 2002 | DAC | Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2002 | DATE | Efficient Wrapper/TAM Co-Optimization for Large SOCs. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2002 | ITC | Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. | Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2002 | ITC | On the Use of k-tuples for SoC Test Schedule Representation. | Sandeep Koranne, Vikram Iyengar |
| 2002 | ITC | A Set of Benchmarks fo Modular Testing of SOCs. | Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty |
| 2002 | VTS | On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2001 | ITC | Test wrapper and test access mechanism co-optimization for system-on-chip. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2001 | VTS | Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. | Vikram Iyengar, Krishnendu Chakrabarty |
| 2000 | PDPTA | Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. | Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara |
| 1999 | VTS | Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar |
| 1998 | VTS | Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray |