| 2020 | DSD | Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. | Luks Kekely, Jakub Cabal, Viktor Pus, Jan Korenek |
| 2018 | FPGA | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2018 | ICNP | Verification of Generated RTL from P4 Source Code. | Radek Isa, Pavel Bencek, Viktor Pus |
| 2017 | FPL | Line rate programmable packet processing in 100Gb networks. | Pavel Bencek, Viktor Pus, Jan Korenek, Michal Kekely |
| 2016 | CNSM | Building a feedback loop to capture evidence of network incidents. | Zdenek Rosa, Toms Cejka, Martin Zdnk, Viktor Pus |
| 2016 | FCCM | P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. | Pavel Bencek, Viktor Pus, Hana Kubtov |
| 2015 | IM | Hardware accelerated flow measurement of 100 Gb ethernet. | Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minark |
| 2015 | IM | High-density network flow monitoring. | Petr Velan, Viktor Pus |
| 2014 | DDECS | Design methodology of configurable high performance packet parser for FPGA. | Viktor Pus, Lukas Kekely, Jan Korenek |
| 2014 | DDECS | CRC based hashing in FPGA using DSP blocks. | Toms Zvodnk, Lukas Kekely, Viktor Pus |
| 2014 | DSD | Architecture of Effective High-Speed Network Stream Merger. | Pavel Bencek, Hana Kubtov, Viktor Pus |
| 2014 | FPGA | Application specific processor with high level synthesized instructions (abstract only). | Viktor Pus, Pavel Bencek |
| 2014 | FPGA | Using DSP blocks to compute CRC hash in FPGA (abstract only). | Viktor Pus, Lukas Kekely, Toms Zvodnk |
| 2014 | FPL | Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. | Lukas Kekely, Viktor Pus, Pavel Bencek, Jan Korenek |
| 2014 | INFOCOM | Software Defined Monitoring of application protocols. | Lukas Kekely, Viktor Pus, Jan Korenek |
| 2012 | IWCMC | Reducing memory in high-speed packet classification. | Viktor Pus, Jan Korenek |
| 2011 | DDECS | Hardware architecture for packet classification with prefix coloring. | Viktor Pus, Michal Kajan, Jan Korenek |
| 2010 | DDECS | Memory optimizations for packet classification algorithms in FPGA. | Viktor Pus, Juraj Blaho, Jan Korenek |
| 2009 | FPGA | Fast and scalable packet classification using perfect hash functions. | Viktor Pus, Jan Korenek |