| 2020 | FPGA | Xilinx Vitis Unified Software Platform. | Vinod Kathail |
| 2016 | FPGA | SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. | Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo |
| 2010 | FPGA | Programming high performance signal processing systems in high level languages. | Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro |
| 2008 | VLSID | Architecture Exploration for Low Power Design. | Vinod Kathail, Tom Miller |
| 2007 | VLSID | Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. | Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar |
| 1999 | PDPTA | Fine Grained Register Allocation for EPIC Processors With Predication. | Hansoo Kim, Vinod Kathail, Kanchi Gopinath, Bhagirath Narahari |
| 1996 | MICRO | Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. | Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich |
| 1995 | MICRO | Critical path reduction for scalar programs. | Michael S. Schlansker, Vinod Kathail |
| 1994 | MICRO | Height reduction of control recurrences for ILP processors. | Michael S. Schlansker, Vinod Kathail, Sadun Anik |