Vishal Suthar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2004–2006
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | DATE | Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. | Vishal Suthar, Shantanu Dutt |
| 2006 | ICCAD | A network-flow approach to timing-driven incremental placement for ASICs. | Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar |
| 2006 | VTS | Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. | Vishal Suthar, Shantanu Dutt |
| 2004 | DAC | Efficient on-line testing of FPGAs with provable diagnosabilities. | Vinay Verma, Shantanu Dutt, Vishal Suthar |