Walid A. Najjar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
58
Venues
29
Active years
1987–2020
Best venue rank
A*
Where they publish
- NationalFCCM8 papers
- BFPL8 papers
- Journal PublishedCASES4 papers
- A*MICRO3 papers
- ACIDR2 papers
- AICCAD2 papers
- A*VLDB2 papers
- A*ICDE2 papers
- ADATE2 papers
- CICCD2 papers
- AFPGA2 papers
- AISLPED2 papers
- A*ISCA2 papers
- BMASCOTS2 papers
- BPADS1 paper
- CDaMoN1 paper
- A*DAC1 paper
- ASC1 paper
- A*ICDM1 paper
- AFAST1 paper
- UnrankedSENSYS1 paper
- BSECON1 paper
- NationalHiPC1 paper
- CICVS1 paper
- NationalPDPTA1 paper
- AICS1 paper
- BSRDS1 paper
- AICDCS1 paper
- BICPP1 paper
Papers
58 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | FCCM | High-Performance Parallel Radix Sort on FPGA. | Bashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar |
| 2017 | PADS | PDES-A: a Parallel Discrete Event Simulation Accelerator for FPGAs. | Shafiur Rahman, Nael B. Abu-Ghazaleh, Walid A. Najjar |
| 2016 | DaMoN | FPGA-accelerated group-by aggregation using synchronizing caches. | Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras |
| 2016 | FPL | Preface. | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
| 2016 | FPL | Optimizing hardware design for Human Action Recognition. | Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury |
| 2015 | CIDR | FPGA-based Multithreading for In-Memory Hash Joins. | Robert J. Halstead, Ildar Absalyamov, Walid A. Najjar, Vassilis J. Tsotras |
| 2015 | ICCAD | CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. | Skyler Windh, Prerna Budhkar, Walid A. Najjar |
| 2014 | FCCM | High-Throughput Fixed-Point Object Detection on FPGAs. | Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury |
| 2013 | CASES | Compiled multithreaded data paths on FPGAs for dynamic workloads. | Robert J. Halstead, Walid A. Najjar |
| 2013 | DAC | FPGA code accelerators - the compiler perspective. | Walid A. Najjar, Jason R. Villarreal |
| 2013 | FCCM | A High Throughput No-Stall Golomb-Rice Hardware Decoder. | Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan |
| 2013 | VLDB | High-Performance XML Twig Filtering using GPUs. | Ildar Absalyamov, Roger Moussalli, Vassilis J. Tsotras, Walid A. Najjar |
| 2011 | FCCM | String Matching in Hardware Using the FM-Index. | Edward Fernandez, Walid A. Najjar, Stefano Lonardi |
| 2011 | ICDE | Massively parallel XML twig filtering using dynamic programming on FPGAs. | Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras |
| 2011 | SC | Exploring irregular memory accesses on FPGAs. | Robert J. Halstead, Jason R. Villarreal, Walid A. Najjar |
| 2011 | VLDB | Efficient XML Path Filtering Using GPUs. | Roger Moussalli, Robert J. Halstead, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras |
| 2010 | FCCM | Designing Modular Hardware Accelerators in C with ROCCC 2.0. | Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert J. Halstead |
| 2010 | FPL | Exploration of Short Reads Genome Mapping in Hardware. | Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi |
| 2010 | ICDM | Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs. | Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamonn J. Keogh, Vit Niennattrakul |
| 2009 | CIDR | Boosting XML filtering through a scalable FPGA-based architecture. | Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Vassilis J. Tsotras, Walid A. Najjar |
| 2008 | FPL | Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. | Betul Buyukkurt, Walid A. Najjar |
| 2008 | FPL | Compiled hardware acceleration of Molecular Dynamics code. | Jason R. Villarreal, Walid A. Najjar |
| 2007 | CASES | Compiling code accelerators for FPGAs. | Walid A. Najjar |
| 2007 | DATE | A one-shot configurable-cache tuner for improved energy and performance. | Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros |
| 2007 | FPL | Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. | Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid |
| 2006 | FPL | Automation of IP Core Interface Generation for Reconfigurable Computing. | Zhi Guo, Abhishek Mitra, Walid A. Najjar |
| 2006 | FPL | A Compiler Intermediate Representation for Reconfigurable Fabrics. | Zhi Guo, Walid A. Najjar |
| 2006 | ICCAD | A code refinement methodology for performance-improved synthesis from C. | Greg Stitt, Frank Vahid, Walid A. Najjar |
| 2006 | ICCD | Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. | Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar |
| 2005 | DATE | Optimized Generation of Data-Path from C Codes for FPGAs. | Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers |
| 2005 | FAST | MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. | Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar |
| 2005 | FPGA | Techniques for synthesizing binaries to an advanced register/memory structure. | Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid |
| 2005 | ICCD | VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. | Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang |
| 2005 | ICDE | Data Acquisition in Sensor Networks with Large Memories. | Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar |
| 2005 | ISLPED | A tunable bus encoder for off-chip data buses. | Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar |
| 2005 | SENSYS | Splitting the sensor node. | Anirban Banerjee, Anirban Mitra, Walid A. Najjar |
| 2005 | SECON | RISE - Co-S : high performance sensor storage and Co-processing architecture. | Anirban Banerjee, Abhishek Mitra, Walid A. Najjar, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos |
| 2004 | FPGA | A quantitative analysis of the speedup factors of FPGAs over processors. | Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers |
| 2004 | ISLPED | A way-halting cache for low-energy high-performance systems. | Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar |
| 2003 | CASES | Power efficient encoding techniques for off-chip data buses. | Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan |
| 2003 | HiPC | FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. | Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar |
| 2003 | ISCA | A Highly-Configurable Cache Architecture for Embedded Systems. | Chuanjun Zhang, Frank Vahid, Walid A. Najjar |
| 2002 | FCCM | Compiling ATR Probing Codes for Execution on FPGA Hardware. | A. P. Wim Bhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar |
| 2002 | FCCM | Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. | Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi |
| 2001 | CASES | A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. | Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Bhm |
| 2001 | FCCM | One-Step Compilation of Image Processing Applications to FPGAs. | A. P. Wim Bhm, Bruce A. Draper, Walid A. Najjar, Jeffrey Hammes, Robert Rinker, Monica Chawathe, Charlie Ross |
| 2001 | ICVS | Compiling SA-C Programs to FPGAs: Performance Results. | Bruce A. Draper, A. P. Wim Bhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, Jos Bins |
| 2000 | PDPTA | A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. | Jeffrey Hammes, Robert Rinker, A. P. Wim Bhm, Walid A. Najjar, Bruce A. Draper |
| 1996 | MASCOTS | Analysis of Buffer Design for Adaptive Routing in Direct Networks. | Annette Lagman, Walid A. Najjar |
| 1995 | MICRO | Design of storage hierarchy in multithreaded architectures. | Lucas Roh, Walid A. Najjar |
| 1994 | ICS | A model for dataflow based vector execution. | William Marcus Miller, Walid A. Najjar, A. P. Wim Bhm |
| 1994 | MASCOTS | Modeling Adaptive Routing in | Walid A. Najjar, Annette Lagman, Sumit Sur, Pradip K. Srimani |
| 1993 | MICRO | An evaluation of bottom-up and top-down thread generation techniques. | A. P. Wim Bhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh |
| 1992 | ISCA | An Analysis of Loop Latency in Dataflow Execution. | Walid A. Najjar, William Marcus Miller, A. P. Wim Bhm |
| 1991 | MICRO | A Quantitative Analysis of Locality in Dataflow Programs. | William Marcus Miller, Walid A. Najjar, A. P. Wim Bhm |
| 1989 | SRDS | Limits on Scalability in Gracefully Degradable Large-Scale Systems. | Walid A. Najjar, Jean-Luc Gaudiot |
| 1988 | ICDCS | Network Disconnection in Distributed Systems. | Walid A. Najjar, Jean-Luc Gaudiot |
| 1987 | ICPP | Multi-Level Execution In Data-Flow Architectures. | Walid A. Najjar, Jean-Luc Gaudiot |