| 2026 | ISCA | Revisiting Global Value Prediction: A Resurgent Complement to Local Predictors. | Ling Yang, Libo Huang, Zhong Zheng, Bingcai Sui, Sheng Ma, Yongwen Wang, Li Shen, Junhui Wang, Gang Chen, Qianming Yang, Songwen Pei, Weixia Xu |
| 2026 | ISCAS | A Power Efficient and Fast Response Cascode FVF LDO Using Voltage Detecting and GB Enhancing Techniques for Cryogenic Quantum Computing. | Chengzhuo Zhao, Mingche Lai, Fangxu Lv, Weixia Xu, Heng Huang, Kewei Xin, Wenchen Wang, Meng Li, Chaolong Xu, Jiliang Liu |
| 2026 | ISCAS | A Capacitor-Less Current-Feedback LDO with Mismatch Cancellation Using DEM and Chopping for Distributed Power Management. | Chengzhuo Zhao, Mingche Lai, Fangxu Lv, Jiaqing Xu, Xingyun Qi, Weixia Xu, Kewei Xin, Wenchen Wang, Jiliang Liu, Zhenyang Zhang |
| 2025 | DATE | ASNPC: An Automated Generation Framework for SNN and Neuromorphic Processor Co-Design. | Xiangyu Wang, Yuan Li, Zhijie Yang, Chao Xiao, Xun Xiao, Renzhi Chen, Weixia Xu, Lei Wang |
| 2025 | IJCAI | BTPG: A Platform and Benchmark for Behavior Tree Planning in Everyday Service Robots. | Xinglin Chen, Yishuai Cai, Minglong Li, Yunxin Mao, Zhou Yang, Wenjing Yang, Weixia Xu, Ji Wang |
| 2024 | DATE | LLM-Based Processor Verification: A Case Study for Neuronnorphic Processor. | Chao Xiao, Yifei Deng, Zhijie Yang, Renzhi Chen, Hong Wang, Jingyue Zhao, Huadong Dai, Lei Wang, Yuhua Tang, Weixia Xu |
| 2024 | ICCD | MOTPE/D: Hardware and Algorithm Co-design for Reconfigurable Neuromorphic Processor. | Yuan Li, Renzhi Chen, Zhijie Yang, Xun Xiao, Jingyue Zhao, Zhenhua Zhu, Huadong Dai, Yuhua Tang, Weixia Xu, Li Luo, Lei Wang |
| 2024 | IJCAI | Integrating Intent Understanding and Optimal Behavior Planning for Behavior Tree Generation from Human Instructions. | Xinglin Chen, Yishuai Cai, Yunxin Mao, Minglong Li, Wenjing Yang, Weixia Xu, Ji Wang |
| 2022 | DAC | Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons. | Zhijie Yang, Lei Wang, Yao Wang, LingHui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, Weixia Xu |
| 2021 | HPCC | Advanced Architecture Design of High-Radix Router Based on Chiplet Integration and IP Reusability. | Chongshan Liang, Yi Dai, Weixia Xu, Qiong Li |
| 2020 | ASPDAC | HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor. | Shasha Guo, Ziyang Kang, Lei Wang, Shiming Li, Weixia Xu |
| 2020 | HPCC | Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network. | Chao Wang, Weixia Xu, Mingche Lai, Jijun Cao |
| 2020 | NPC | CompressedCache: Enabling Storage Compression on Neuromorphic Processor for Liquid State Machine. | Zhijie Yang, Rui Gong, Lianhua Qu, Ziyang Kang, Li Luo, Lei Wang, Weixia Xu |
| 2019 | NPC | PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array. | Shuquan Wang, Lei Wang, Shiming Li, Shuo Tian, Shasha Guo, Ziyang Kang, Shuzheng Zhang, Weixia Xu |
| 2017 | ISPA | Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks. | Naiyang Guan, Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang |
| 2016 | ICA3PP | Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration. | Jie Jian, Mingche Lai, Liquan Xiao, Weixia Xu |
| 2015 | IPCCC | A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor. | Jinbo Xu, Weixia Xu, Zhengbin Pang |
| 2014 | AICCSA | Fast NIC based RDMA implementation for adaptive unreliable networks. | Shaogang Wang, Weixia Xu, Dan Wu, Zhengbin Pang |
| 2014 | IPCCC | Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor. | Jinbo Xu, Weixia Xu, Kefei Wang, Zhengbin Pang |
| 2012 | HPCC | Optimizing Private Memory Performance by Dynamically Deactivating Cache Coherence. | Shaogang Wang, Weixia Xu, Zhengbin Pang, Dan Wu, Yi Dai, Pingjing Lu |
| 2012 | ICA3PP | Frame Error Rate Testing for High Speed Optical Interconnect. | Yi Dai, Kefei Wang, Weixia Xu, Heying Zhang, Shaogang Wang |
| 2011 | HPCC | A Parallel Processing Scheme for Large-Size Sliding-Window Applications. | Weixia Xu, Jinbo Xu, Zhengbin Pang |
| 2011 | ICCD | A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer. | Wei Shi, Weixia Xu, Hongguang Ren, Qiang Dou, Zhiying Wang, Li Shen, Cong Liu |
| 2011 | IDEAL | Finding First-Order Minimal Unsatisfiable Cores with a Heuristic Depth-First-Search Algorithm. | Jianmin Zhang, Weixia Xu, Jun Zhang, ShengYu Shen, Zhengbin Pang, Tiejun Li, Jun Xia, Sikun Li |
| 2010 | ICPADS | A Novel Chaining Approach for Direct Control Transfer Instructions. | Weixia Xu, Wei Chen, Qiang Dou |
| 2009 | ICPP | DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System. | Shaogang Wang, Weixia Xu, Zhengbin Pang, Dan Wu, Qiang Dou, Xiaodong Yang |
| 2009 | ISCC | An efficient stream memory architecture for heterogeneous multicore processor. | Rangyu Deng, Weixia Xu, Qiang Dou, Hongwei Zhou, Zefu Dai, Haiyan Chen |