| 2025 | DAC | NN-AdderNet: Nonnegative and Sparse Weight Optimization Towards Ultra-Low Bitwidth AdderNet Quantization and Compression. | Yunxiang Zhang, Gengchen Sun, Lizhi Fang, Biao Sun, Wenfeng Zhao |
| 2025 | FCCM | BCIM: A Bit-Serial Approach for Block-Cipher-in-Memory. | Andrew Dervay, Omar Al Kailani, Wenfeng Zhao |
| 2025 | ICCAD | JSA-CIM: A Joint-Sparse AdderNet Compute-In-Memory Accelerator for Energy-Efficient Edge AI Applications. | Omar Al Kailani, Yunxiang Zhang, Wenfeng Zhao |
| 2025 | ICCAD | Non-Negative AdderNet: Algorithm-Hardware Co-design for Lightweight Defense of Adversarial Bit-Flip Attacks. | Yunxiang Zhang, Sabbir Ahmed, Abeer Matar A. Almalky, Adnan Siraj Rakin, Wenfeng Zhao |
| 2025 | ICDM | Parameterized Hardware Generation for Mini-Float Summation-of-Absolute-Differences for AdderNet Based CNN Models. | Spencer Miles Buchanan, Jose Ramos, Cameron D. DiSomma, Yunxiang Zhang, Wenfeng Zhao, Xiaokun Yang |
| 2024 | DAC | AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization. | Yunxiang Zhang, Omar Al Kailani, Wenfeng Zhao |
| 2023 | DASFAA | Deep Normalization Cross-Modal Retrieval for Trajectory and Image Matching. | Xudong Zhang, Wenfeng Zhao |
| 2022 | ICCAD | WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. | Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao |
| 2022 | ICPR | Nonuniform illumination correction for underwater images through a pseudo-siamese network. | Wenfeng Zhao, Shenghui Rong, Jiankang Ma, Bo He |
| 2022 | ISCAS | Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design. | Yunxiang Zhang, Jian Xu, Miao Hu, Wenfeng Zhao |
| 2019 | ACSSC | Block-Sparse Modeling for Compressed Sensing of Neural Action Potentials and Local Field Potentials. | Wenfeng Zhao, Tong Wu, Jian Xu, Qi Zhao, Zhi Yang |
| 2017 | MICRO | BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors. | Ang Li, Wenfeng Zhao, Shuaiwen Leon Song |
| 2015 | ISCAS | AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. | Wenfeng Zhao, Yajun Ha, Massimo Alioto |
| 2013 | FPL | Criticality-based routing for FPGAS with reverse body bias switch box architectures. | Wei Ting Loke, Wenfeng Zhao, Yajun Ha |
| 2013 | ISLPED | Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. | Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez |
| 2008 | ICWS | Integrating Information-Providing Web Services into the Data Integration System. | Wenfeng Zhao, Xiangwu Meng, Junliang Chen, Chuanchang Liu |