| 2017 | DDECS | A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology. | Michal Wolodzko, Wieslaw Kuzmicz |
| 2011 | DSD | Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. | Michal Bryk, Lech Jzwiak, Wieslaw Kuzmicz |
| 2008 | DSD | Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. | Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz |
| 2005 | DSD | Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | ETS | DOT: new deterministic defect-oriented ATPG tool. | Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2002 | DSD | Integrated Design and Test Generation Under Internet Based Environment MOSCITO. | Andr Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatov, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng |
| 2000 | ETS | Hierarchical defect-oriented fault simulation for digital circuits. | Mykola Blyzniuk, T. Cibkov, Elena Gramatov, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar |
| 1997 | VTS | Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. | Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz |
| 1995 | DATE | SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. | Witold A. Pleskacz, Wieslaw Kuzmicz |