| 2023 | ICNC | Neonatal Hypoxic-ischemic Encephalopathy Grading from Multi-channel EEG Time-series Data Using a Fully Convolutional Neural Network. | Shuwen Yu, William P. Marnane, Geraldine B. Boylan, Gordon Lightbody |
| 2017 | BSN | Android based warning system for the early detection of allergic reactions. | Estefania Munoz Diaz, Raquel Gutierrez-Rivas, Juan Jess Garca, William P. Marnane, Ana Jimnez, David Gualda |
| 2014 | ICASSP | Grading brain injury in neonatal EEG using SVM and supervector kernel. | Rehan Ahmed, Andrey Temko, William P. Marnane, Geraldine B. Boylan, Gordon Lightbody |
| 2014 | ICASSP | Modulation frequency analysis of seizures in neonatal EEG. | Andrey Temko, Geraldine B. Boylan, William P. Marnane, Gordon Lightbody |
| 2014 | ICASSP | EEG 'diarization' for the description of neonatal brain injuries. | Andrey Temko, William P. Marnane, Geraldine B. Boylan, Gordon Lightbody |
| 2011 | FPL | A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values. | Mark Hamilton, William P. Marnane, Arnaud Tisserand |
| 2010 | FPL | FPGA Implementations of the Round Two SHA-3 Candidates. | Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Mire O'Neill, William P. Marnane |
| 2009 | DSD | FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. | Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane |
| 2009 | WISA | Unknown Plaintext Template Attacks. | Neil Hanley, Michael Tunstall, William P. Marnane |
| 2007 | WISA | Differential Power Analysis of HMAC Based on SHA-2, and Countermeasures. | Robert P. McEvoy, Michael Tunstall, Colin C. Murphy, William P. Marnane |
| 2006 | FPL | FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences. | Mara del Carmen Prez, Jess Urea, lvaro Hernndez, Carlos De Marziani, Alberto Ochoa, William P. Marnane |
| 2005 | CHES | Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. | Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto |
| 2005 | FPL | FPGA Implementation of a GF(2 | Maurice Keller, Tim Kerins, William P. Marnane |
| 2004 | FPL | Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. | Tim Kerins, Emanuel M. Popovici, William P. Marnane |
| 2003 | FPL | Fast Modular Division for Application in ECC on Reconfigurable Logic. | Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici |
| 2002 | FPGA | Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. | Alan Daly, William P. Marnane |
| 2002 | FPL | Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). | Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick |
| 2001 | ISCAS | A regular parallel multiplier which utilizes multiple carry-propagate adders. | Henrik Eriksson, Per Larsson-Edefors, William P. Marnane |
| 2000 | FPL | A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. | Stephen J. Bellis, William P. Marnane |
| 1999 | ICASSP | Parametric spectral estimation on a single FPGA. | Stephen J. Bellis, William P. Marnane, Peter J. Fish |
| 1995 | FPL | Compiling Regular Arrays onto FPGAs. | William P. Marnane, C. N. Jordan, F. J. O'Reilly |
| 1991 | ICASSP | Design and test of a bit parallel 2nd order IIR filter structure. | O. C. McNally, William P. Marnane, John V. McCanny |
| 1988 | ICCD | Testing of VLSI regular arrays. | William P. Marnane, Will R. Moore |