Wolfgang Fichtner
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
34
Venues
12
Active years
1988–2011
Best venue rank
A*
Where they publish
Papers
34 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | SC | Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s. | Mathieu Luisier, Timothy B. Boykin, Gerhard Klimeck, Wolfgang Fichtner |
| 2010 | ETS | Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. | Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner |
| 2009 | DATE | Hardware evaluation of the stream cipher-based hash functions RadioGatn and irRUPT. | Luca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner |
| 2009 | ETS | Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications. | Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner |
| 2009 | ISCAS | VLSI Implementations of the Cryptographic Hash Functions MD6 and rRUPT. | Luca Henzen, Flavio Carbognani, Jean-Philippe Aumasson, Sean O'Neil, Wolfgang Fichtner |
| 2009 | ISCAS | Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed. | Markus Wenk, Peter Luethi, Thomas Koch, Patrick Maechler, Norbert Felber, Wolfgang Fichtner, Michael Lerjen |
| 2009 | ISCAS | Live Demonstration: Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed. | Markus Wenk, Peter Luethi, Thomas Koch, Patrick Maechler, Norbert Felber, Wolfgang Fichtner, Michael Lerjen |
| 2008 | EuroPar | A Parallel Sparse Linear Solver for Nearest-Neighbor Tight-Binding Problems. | Mathieu Luisier, Gerhard Klimeck, Andreas Schenk, Wolfgang Fichtner, Timothy B. Boykin |
| 2008 | ISCAS | Hardware-efficient steering matrix computation architecture for MIMO communication systems. | Christian Senning, Christoph Studer, Peter Luethi, Wolfgang Fichtner |
| 2008 | ISCAS | VLSI architecture for data-reduced steering matrix feedback in MIMO systems. | Christoph Studer, Peter Luethi, Wolfgang Fichtner |
| 2008 | MOBICOM | Multi-user MIMO testbed. | Peter Luethi, Markus Wenk, Thomas Koch, Wolfgang Fichtner, Michael Lerjen, Norbert Felber |
| 2007 | ISCAS | Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation. | Andreas Burg, Simon Haene, Wolfgang Fichtner, Markus Rupp |
| 2007 | ISCAS | FFT Processor for OFDM Channel Estimation. | Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner |
| 2007 | ISCAS | VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. | Peter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner |
| 2007 | ISCAS | Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems. | David Perels, Christoph Studer, Wolfgang Fichtner |
| 2007 | ISCAS | Wireless Implant Communications for Biomedical Monitoring Sensor Network. | Marc Simon Wegmueller, Martin Hediger, Thomas Kaufmann, Felix Brgin, Wolfgang Fichtner |
| 2006 | DAC | Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. | Felix Brgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner |
| 2006 | DATE | Two-phase resonant clocking for ultra-low-power hearing aid applications. | Flavio Carbognani, Felix Brgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
| 2006 | ICASSP | A Frame-Start Detector for a 44 MIMO-OFDM System. | David Perels, Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner |
| 2006 | ISCAS | Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. | Andreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner |
| 2006 | ISCAS | 42% power savings through glitch-reducing clocking strategy in a hearing aid application. | Flavio Carbognani, Felix Brgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
| 2006 | ISCAS | Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. | Simon Haene, Andreas Burg, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner |
| 2006 | ISCAS | K-best MIMO detection VLSI architectures achieving up to 424 Mbps. | Markus Wenk, Martin Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner |
| 2003 | ISCAS | Variable delay ripple carry adder with carry chain interrupt detection. | Andreas Burg, Frank K. Grkaynak, Hubert Kaeslin, Wolfgang Fichtner |
| 2002 | CHES | 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. | Adrian K. Lutz, Jrg Treichler, Frank K. Grkaynak, Hubert Kaeslin, Grard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner |
| 2001 | ISCAS | A new approach for controlling series-connected IGBT modules. | Jan Thalheim, Norbert Felber, Wolfgang Fichtner |
| 1999 | ITC | Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. | Manfred Stadler, Thomas Rwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann |
| 1993 | ITC | VINCI: Secure Test of a VLSI High-Speed Encryption System. | Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Reto Zimmermann, Wolfgang Fichtner |
| 1992 | ICCAD | Lazy-expansion symbolic expression approximation in SYNAP. | Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner |
| 1991 | SC | PILS: an iterative linear solver package for ill-conditioned systems. | Claude Pommerell, Wolfgang Fichtner |
| 1989 | DAC | An Analytic Optimization Technique for Placement of Macro-Cells. | Alexander Herrigel, Wolfgang Fichtner |
| 1989 | ICCD | A global floorplanning technique for VLSI layout. | Alexander Herrigel, M. Glaser, Wolfgang Fichtner |
| 1989 | ICCD | Macrocell-level compaction with automatic jog introduction. | Alexander Herrigel, J. Kamm, Wolfgang Fichtner |
| 1988 | ICCAD | A symbolic analysis tool for analog circuit design automation. | Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner |