| 2025 | AAAI | Int2Planner: An Intention-based Multi-modal Motion Planner for Integrated Prediction and Planning. | Xiaolei Chen, Junchi Yan, Wenlong Liao, Tao He, Pai Peng |
| 2025 | DASFAA | Log Parsing with LLMs Featuring Self-reflection and Continuous Refining. | Xiaolei Chen, Jia Chen, Jie Shi, Peng Wang, Wei Wang |
| 2025 | FASE | VOCE: A Virtual On-Call Engineer for Automated Alert Incident Analysis Using a Large Language Model. | Jia Chen, Xiaolei Chen, Jie Shi, Peng Wang, Wei Wang |
| 2025 | ICDE | EPAS: Efficient Online Log Parsing via Asynchronous Scheduling of LLM Queries. | Xiaolei Chen, Jia Chen, Jie Shi, Peng Wang, Wei Wang |
| 2024 | ICSE | High-precision Online Log Parsing with Large Language Models. | Xiaolei Chen, Jie Shi, Jia Chen, Peng Wang, Wei Wang |
| 2023 | IECON | Analysis and Suppression Method of Motor Current Fluctuation Caused by DC-Link Voltage Ripple in PMSM Drives. | Tao Li, Chaohui Liang, Hongbo Wang, Haijun Xie, Xiaolei Chen |
| 2020 | ICPR | Compressed Video Action Recognition Using Motion Vector Representation. | Chenghui Zhou, Xiaolei Chen, Pei Sun, Guanwen Zhang, Wei Zhou |
| 2020 | ICPR | Deep Reinforcement Learning for Autonomous Driving by Transferring Visual Features. | Hongli Zhou, Xiaolei Chen, Guanwen Zhang, Wei Zhou |
| 2017 | IROS | Rearranging agents in a small space using global controls. | Yinan Zhang, Xiaolei Chen, Hang Qi, Devin J. Balkcom |
| 2015 | ICNC | Performance optimization of the echo state network for time series prediction and spoken digit recognition. | Qingchun Zhao, Hongxi Yin, Xiaolei Chen, Wenbo Shi |
| 2009 | FPL | sFPGA2 - A scalable GALS FPGA architecture and design methodology. | Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli |
| 2008 | FCCM | An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. | Hanyu Liu, Xiaolei Chen, Yajun Ha |
| 2008 | FPL | sFPGA - A scalable switch based FPGA architecture and design methodology. | Shakith Fernando, Xiaolei Chen, Yajun Ha |
| 2008 | FPL | An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. | Hanyu Liu, Xiaolei Chen, Yajun Ha |