| 2016 | ISLPED | Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. | Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu |
| 2015 | ASPDAC | An efficient STT-RAM-based register file in GPU architectures. | Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen |
| 2014 | ICCD | Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. | Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li |
| 2014 | ISLPED | Design exploration of racetrack lower-level caches. | Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li |
| 2013 | DATE | STT-RAM designs supporting dual-port accesses. | Xiuyuan Bi, Mohamed Anis Weldon, Hai Li |
| 2013 | ICCAD | Unleashing the potential of MLC STT-RAM caches. | Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li |
| 2012 | DATE | Spintronic memristor based temperature sensor design with CMOS current reference. | Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino |
| 2012 | ICCAD | Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. | Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu |
| 2012 | ISLPED | Process variation aware data management for STT-RAM cache design. | Zhenyu Sun, Xiuyuan Bi, Hai Li |
| 2011 | MICRO | Multi retention level STT-RAM cache designs with a dynamic refresh scheme. | Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu |