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Xuechao Wei

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

17

Venues

9

Active years

2012–2024

Best venue rank

A*

Where they publish

Papers

17 indexed papers, newest first.

YearVenueTitleAuthors
2024DACPT-Map: Efficient Program Transformation Optimization for CGRA Mapping.Bizhao Shi, Tuo Dai, Jiaxi Zhang, Xuechao Wei, Guojie Luo
2024ICSRadiK: Scalable and Optimized GPU-Parallel Radix Top-K Selection.Yifei Li, Bole Zhou, Jiejing Zhang, Xuechao Wei, Yinghan Li, Yingda Chen
2024PPoPPPOSTER: RadiK: Scalable Radix Top-K Selection on GPUs.Yifei Li, Bole Zhou, Jiejing Zhang, Xuechao Wei, Yinghan Li, Yingda Chen
2023ICCADKlotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators.Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie
2023MICROArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.Chen Bai, Jiayi Huang, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu, Yuan Xie
2022ICCAD2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration.Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie
2022USENIXPetS: A Unified Framework for Parameter-Efficient Transformers Serving.Zhe Zhou, Xuechao Wei, Jiejing Zhang, Guangyu Sun
2020DACFTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability.Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding
2020FPGAFTDL: An FPGA-tailored Architecture for Deep Learning Systems.Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding
2019DACOvercoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management.Xuechao Wei, Yun Liang, Jason Cong
2019FPGAOvercoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment.Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong
2019ISCASFrequency Improvement of Systolic Array-Based CNNs on FPGAs.Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong
2018ICCADTGPA: tile-grained pipeline architecture for low latency CNN inference.Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong
2017ASPDACThroughput optimization for streaming applications on CPU-FPGA heterogeneous systems.Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong
2017DACAutomated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs.Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong
2012ICSDistributed replay protocol for distributed uniprocessors.Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han
2012PPoPPFlexBFS: a parallelism-aware implementation of breadth-first search on GPU.Gu Liu, Hong An, Wenting Han, Xiaoqiang Li, Tao Sun, Wei Zhou, Xuechao Wei, Xulong Tang