| 2025 | ISCA | Enabling Ahead Prediction with Practical Energy Constraints. | Lingzhe Chester Cai, Aniket Deshmukh, Yale N. Patt |
| 2024 | ISCA | Alternate Path Fetch. | Aniket Deshmukh, Lingzhe Chester Cai, Yale N. Patt |
| 2024 | MICRO | Timely, Efficient, and Accurate Branch Precomputation. | Aniket Deshmukh, Lingzhe Chester Cai, Yale N. Patt |
| 2022 | HPCA | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection. | Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi |
| 2021 | MICRO | Criticality Driven Fetch. | Aniket Deshmukh, Yale N. Patt |
| 2021 | MICRO | Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches. | Stephen Pruett, Yale N. Patt |
| 2020 | ISCA | Tailored Page Sizes. | Faruk Guvenilir, Yale N. Patt |
| 2020 | MICRO | BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches. | Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt |
| 2018 | MICRO | Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. | Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt |
| 2016 | ISCA | Accelerating Dependent Cache Misses with an Enhanced Memory Controller. | Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt |
| 2016 | MICRO | Continuous runahead: Transparent hardware acceleration for memory intensive workloads. | Milad Hashemi, Onur Mutlu, Yale N. Patt |
| 2015 | MICRO | Filtered runahead execution with a runahead buffer. | Milad Hashemi, Yale N. Patt |
| 2014 | ICS | Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. | Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt |
| 2013 | ISCA | Utility-based acceleration of multithreaded applications on asymmetric CMPs. | Jos A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
| 2012 | ASPLOS | Bottleneck identification and scheduling in multithreaded applications. | Jos A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
| 2012 | ICS | High performance supercomputers: should the individual processor be more than a brick? | Yale N. Patt |
| 2012 | MICRO | MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. | Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt |
| 2012 | MICRO | Predicting Performance Impact of DVFS for Realistic Memory Systems. | Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt |
| 2012 | SBAC-PAD | Energy Savings via Dead Sub-Block Prediction. | Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt |
| 2011 | ISCA | Prefetch-aware shared resource management for multi-core systems. | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt |
| 2011 | MICRO | Parallel application memory scheduling. | Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2011 | MICRO | Improving GPU performance via large warps and two-level warp scheduling. | Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt |
| 2010 | ASPLOS | Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt |
| 2010 | ISCA | Data marshaling for multi-core architectures. | M. Aater Suleman, Onur Mutlu, Jos A. Joao, Khubaib, Yale N. Patt |
| 2009 | ASPLOS | Accelerating critical section execution with asymmetric multi-core architectures. | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt |
| 2009 | HPCA | Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. | Eiman Ebrahimi, Onur Mutlu, Yale N. Patt |
| 2009 | HPCA | Multi-core demands multi-interfaces. | Yale N. Patt |
| 2009 | ISCA | Flexible reference-counting-based hardware acceleration for garbage collection. | Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2009 | MICRO | Coordinated control of multiple prefetchers in multi-core systems. | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt |
| 2009 | MICRO | Improving memory bank-level parallelism in the presence of prefetching. | Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt |
| 2009 | PPoPP | Multi-core demands multi-interfaces. | Yale N. Patt |
| 2008 | ASPLOS | Improving the performance of object-oriented languages with dynamic predication of indirect jumps. | Jos A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt |
| 2008 | ASPLOS | Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. | M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt |
| 2008 | HPCA | Performance-aware speculation control using wrong path usefulness prediction. | Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
| 2008 | ISCA | Achieving Out-of-Order Performance with Almost In-Order Complexity. | Francis Tseng, Yale N. Patt |
| 2008 | MICRO | Prefetch-Aware DRAM Controllers. | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt |
| 2007 | CGO | Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2007 | HiPC | The Transformation Hierarchy in the Era of Multi-core. | Yale N. Patt |
| 2007 | HPCA | Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. | Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt |
| 2007 | HPCA | Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. | Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2007 | ISCA | VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn |
| 2007 | ISCA | Adaptive insertion policies for high performance caching. | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer |
| 2006 | CGO | 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. | Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt |
| 2006 | ISCA | Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? | Yale N. Patt |
| 2006 | ISCA | A Case for MLP-Aware Cache Replacement. | Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt |
| 2006 | MICRO | Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. | Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt |
| 2006 | MICRO | Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. | Moinuddin K. Qureshi, Yale N. Patt |
| 2005 | AICCSA | The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? | Yale N. Patt |
| 2005 | DSN | Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. | Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt |
| 2005 | ISCA | Techniques for Efficient Processing in Runahead Execution Engines. | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2005 | ISCA | The V-Way Cache: Demand Based Associativity via Global Replacement. | Moinuddin K. Qureshi, David Thompson, Yale N. Patt |
| 2005 | MICRO | Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. | Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt |
| 2005 | MICRO | Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
| 2004 | ISPASS | The future of simulation: A field of dreams. | Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith |
| 2004 | ISPASS | Opening and keynote 1. | Yale N. Patt |
| 2004 | MICRO | Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. | David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt |
| 2004 | SBAC-PAD | Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
| 2003 | HiPC | The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? | Yale N. Patt |
| 2003 | HPCA | Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt |
| 2003 | ICS | Partitioned first-level cache design for clustered microarchitectures. | Paul Racunas, Yale N. Patt |
| 2003 | WCAE | Teaching and teaching computer architecture: two very different topics: (some opinions about each). | Yale N. Patt |
| 2002 | CASES | Handling of packet dependencies: a critical issue for highly parallel network processors. | Stephen W. Melvin, Yale N. Patt |
| 2002 | HPCA | Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. | Mary D. Brown, Yale N. Patt |
| 2002 | ISCA | Difficult-Path Branch Prediction Using Subordinate Microthreads. | Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz |
| 2002 | MICRO | Microarchitectural support for precomputation microthreads. | Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt |
| 2001 | MICRO | Select-free instruction scheduling logic. | Mary D. Brown, Jared Stark, Yale N. Patt |
| 2001 | SIGCSE | Programming early considered harmful. | Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt |
| 2000 | MICRO | On pipelining dynamic instruction scheduling logic. | Jared Stark, Mary D. Brown, Yale N. Patt |
| 1999 | ISCA | Simultaneous Subordinate Microthreading (SSMT). | Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt |
| 1999 | WCAE | Computer architecture education: mechanical engineers need it too. | Yale N. Patt |
| 1998 | ASPLOS | Variable Length Path Branch Prediction. | Jared Stark, Marius Evers, Yale N. Patt |
| 1998 | ISCA | An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. | Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt |
| 1998 | ISCA | Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. | Wen-mei W. Hwu, Yale N. Patt |
| 1998 | ISCA | HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. | Wen-mei W. Hwu, Yale N. Patt |
| 1998 | ISCA | Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. | Sanjay J. Patel, Marius Evers, Yale N. Patt |
| 1998 | ISCA | Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1998 | ISCA | Alternative Implementations of Two-Level Adaptive Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1998 | MICRO | Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt |
| 1997 | ISCA | Target Prediction for Indirect Jumps. | Po-Yung Chang, Eric Hao, Yale N. Patt |
| 1997 | ISCA | The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. | Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt |
| 1997 | MICRO | Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt |
| 1997 | MICRO | Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. | Jared Stark, Paul Racunas, Yale N. Patt |
| 1996 | ISCA | Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. | Marius Evers, Po-Yung Chang, Yale N. Patt |
| 1996 | MICRO | Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. | Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt |
| 1996 | WCAE | Education in computer science and computer engineering starts with computer architecture. | Yale N. Patt |
| 1995 | ICPP | Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays. | Robert Y. Hou, Yale N. Patt |
| 1995 | MICRO | Alternative implementations of hybrid branch predictors. | Po-Yung Chang, Eric Hao, Yale N. Patt |
| 1995 | SIGMETRICS | On-Line Extraction of SCSI Disk Drive Parameters. | Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt, John Wilkes |
| 1995 | WCAE | Components of a computer architecture education. | Yale N. Patt |
| 1995 | WCAE | Components of a computer architecture education: optimal and suboptimal. | Yale N. Patt |
| 1994 | MICRO | Branch classification: a new mechanism for improving branch predictor performance. | Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt |
| 1994 | MICRO | The effect of speculatively updating branch history on branch prediction accuracy, revisited. | Eric Hao, Po-Yung Chang, Yale N. Patt |
| 1994 | MICRO | Facilitating superscalar processing via a combined static/dynamic register renaming scheme. | Eric Sprangle, Yale N. Patt |
| 1994 | OSDI | Metadata Update Performance in File Systems. | Gregory R. Ganger, Yale N. Patt |
| 1994 | SIGMETRICS | Scheduling Algorithms for Modern Disk Drives. | Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt |
| 1993 | HPDC | Trading Disk Capacity for Performance. | Robert Y. Hou, Yale N. Patt |
| 1993 | ISCA | A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. | Tse-Yu Yeh, Yale N. Patt |
| 1993 | ICS | Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. | Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt |
| 1993 | MICRO | A comparative performance evaluation of various state maintenance mechanisms. | Michael Butler, Yale N. Patt |
| 1993 | MICRO | Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. | Tse-Yu Yeh, Yale N. Patt |
| 1993 | SIGMOD | Comparing Rebuild Algorithms for Mirrored and RAID5 Disk Arrays. | Robert Y. Hou, Yale N. Patt |
| 1993 | SIGMETRICS | The Process-Flow Model: Examining I/O Performance from the System's Point of View. | Gregory R. Ganger, Yale N. Patt |
| 1992 | ISCA | Alternative Implementations of Two-Level Adaptive Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1992 | MICRO | An investigation of the performance of various dynamic scheduling techniques. | Michael Butler, Yale N. Patt |
| 1992 | MICRO | A comprehensive instruction fetch mechanism for a processor supporting speculative execution. | Tse-Yu Yeh, Yale N. Patt |
| 1991 | ISCA | Single Instruction Stream Parallelism is Greater Than Two. | Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow |
| 1991 | ISCA | Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. | Stephen W. Melvin, Yale N. Patt |
| 1991 | MICRO | The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. | Michael Butler, Yale N. Patt |
| 1991 | MICRO | Two-Level Adaptive Training Branch Prediction. | Tse-Yu Yeh, Yale N. Patt |
| 1990 | ICPP | An Area-Efficient Register Alias Table for Implementing HPS. | Michael Butler, Yale N. Patt |
| 1989 | ISCA | A High Performance Prolog Processor with Multiple Function Units. | Ashok Singhal, Yale N. Patt |
| 1989 | ICS | Performance benefits of large execution atomic units in dynamically scheduled machines. | Stephen W. Melvin, Yale N. Patt |
| 1989 | MICRO | Microarchitecture choices (implementation of the VAX). | Yale N. Patt |
| 1988 | ICS | Hierarchical registers for scientific computers. | John A. Swensen, Yale N. Patt |
| 1988 | MICRO | Hardware support for large atomic units in dynamically scheduled machines. | Stephen W. Melvin, Michael Shebanow, Yale N. Patt |
| 1988 | MICRO | Implementing a Prolog machine with multiple functional units. | Ashok Singhal, Yale N. Patt |
| 1988 | SIGMETRICS | The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels. | Stephen W. Melvin, Yale N. Patt |
| 1987 | ICLP | Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer. | Jeffrey D. Gee, Stephen W. Melvin, Yale N. Patt |
| 1987 | ISCA | Checkpoint Repair for Out-of-order Execution Machines. | Wen-mei W. Hwu, Yale N. Patt |
| 1987 | ISCA | Fast Temporary Storage for Serial and Parallel Execution. | John A. Swensen, Yale N. Patt |
| 1987 | MICRO | Exploiting horizontal and vertical concurrency via the HPSm microprocessor. | Wen-mei W. Hwu, Yale N. Patt |
| 1987 | MICRO | SPAM: a microcode based tool for tracing operating system events. | Stephen W. Melvin, Yale N. Patt |
| 1987 | MICRO | On tuning the microarchitecture of an HPS implementation of the VAX. | James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt |
| 1986 | ISCA | HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. | Wen-mei W. Hwu, Yale N. Patt |
| 1986 | MICRO | The implementation of Prolog via VAX 8600 microcode. | Jeffrey D. Gee, Stephen W. Melvin, Yale N. Patt |
| 1986 | MICRO | A microcode-based environment for noninvasive performance analysis. | Stephen W. Melvin, Yale N. Patt |
| 1986 | MICRO | Run-time generation of HPS microinstructions from a VAX instruction stream. | Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen |
| 1985 | ISCA | Performance Studies of a Prolog Machine Architecture. | Tep P. Dobry, Alvin M. Despain, Yale N. Patt |
| 1985 | MICRO | Compiling Prolog into microcode: a case study using the NCR/32-000. | Barry S. Fagin, Yale N. Patt, Vason P. Srini, Alvin M. Despain |
| 1985 | MICRO | Microcode and the protection of intellectual effort. | Yale N. Patt, John K. Ahlstrom |
| 1985 | MICRO | HPS, a new microarchitecture: rationale and introduction. | Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow |
| 1985 | MICRO | Critical issues regarding HPS, a high performance microarchitecture. | Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow |
| 1984 | MICRO | Design decisions influencing the microarchitecture for a Prolog machine. | Tep P. Dobry, Yale N. Patt, Alvin M. Despain |
| 1984 | MICRO | Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures. | Carl Ponder, Yale N. Patt |