Yanyue Xie
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
10
Active years
2020–2025
Best venue rank
A*
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference. | Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin |
| 2025 | ICCAD | Squat: Quant Small Language Models on the Edge. | Xuan Shen, Peiyan Dong, Zhenglun Kong, Yifan Gong, Changdi Yang, Zhaoyang Han, Yanyue Xie, Lei Lu, Cheng Lyu, Chao Wu, Yanzhi Wang, Pu Zhao |
| 2024 | DATE | SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum- Flux - Parametron Superconducting Circuits. | Yanyue Xie, Peiyan Dong, Geng Yuan, Zhengang Li, Masoud Zabihi, Chao Wu, Sung-En Chang, Xufeng Zhang, Xue Lin, Caiwen Ding, Nobuyuki Yoshikawa, Olivia Chen, Yanzhi Wang |
| 2024 | FPL | SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs. | Geng Yang, Yanyue Xie, Zhong Jia Xue, Sung-En Chang, Yanyu Li, Peiyan Dong, Jie Lei, Weiying Xie, Yanzhi Wang, Xue Lin, Zhenman Fang |
| 2024 | ICS | Quasar-ViT: Hardware-Oriented Quantization-Aware Architecture Search for Vision Transformers. | Zhengang Li, Alec Lu, Yanyue Xie, Zhenglun Kong, Mengshu Sun, Hao Tang, Zhong Jia Xue, Peiyan Dong, Caiwen Ding, Yanzhi Wang, Xue Lin, Zhenman Fang |
| 2023 | AAAI | Peeling the Onion: Hierarchical Reduction of Data Redundancy for Efficient Vision Transformer Training. | Zhenglun Kong, Haoyu Ma, Geng Yuan, Mengshu Sun, Yanyue Xie, Peiyan Dong, Xin Meng, Xuan Shen, Hao Tang, Minghai Qin, Tianlong Chen, Xiaolong Ma, Xiaohui Xie, Zhangyang Wang, Yanzhi Wang |
| 2023 | DAC | Invited: Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration. | Zhengang Li, Yanyue Xie, Peiyan Dong, Olivia Chen, Yanzhi Wang |
| 2023 | DATE | ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training. | Sung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang, Yanzhi Wang |
| 2023 | HPCA | HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers. | Peiyan Dong, Mengshu Sun, Alec Lu, Yanyue Xie, Kenneth Liu, Zhenglun Kong, Xin Meng, Zhengang Li, Xue Lin, Zhenman Fang, Yanzhi Wang |
| 2023 | MICRO | SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices. | Zhengang Li, Geng Yuan, Tomoharu Yamauchi, Masoud Zabihi, Yanyue Xie, Peiyan Dong, Xulong Tang, Nobuyuki Yoshikawa, Devesh Tiwari, Yanzhi Wang, Olivia Chen |
| 2022 | DAC | Hardware-efficient stochastic rounding unit design for DNN training: late breaking results. | Sung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang, Yanzhi Wang |
| 2022 | DAC | TAAS: a timing-aware analytical strategy for AQFP-capable placement automation. | Peiyan Dong, Yanyue Xie, Hongjia Li, Mengshu Sun, Olivia Chen, Nobuyuki Yoshikawa, Yanzhi Wang |
| 2022 | DAC | FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results. | Mengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang |
| 2022 | ECCV | You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding. | Geng Yuan, Sung-En Chang, Qing Jin, Alec Lu, Yanyu Li, Yushu Wu, Zhenglun Kong, Yanyue Xie, Peiyan Dong, Minghai Qin, Xiaolong Ma, Xulong Tang, Zhenman Fang, Yanzhi Wang |
| 2022 | FPL | Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. | Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang |
| 2021 | DATE | Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. | Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang |
| 2020 | DAC | Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs | Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu, Jianli Chen |