| 2011 | DATE | On routing fixed escaped boundary pins for high speed boards. | Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani |
| 2006 | ISCAS | Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. | Yoji Kajitani |
| 2005 | ISCAS | Fixed-outline floorplanning with constraints through instance augmentation. | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani |
| 2005 | ISCAS | A new approach based on LFF for optimization of dynamic hardware reconfigurations. | Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani |
| 2004 | ASPDAC | Abstraction and optimization of consistent floorplanning with pillar block constraints. | Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani |
| 2004 | ASPDAC | Multi-level placement with circuit schema based clustering in analog IC layouts. | Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani |
| 2004 | ASPDAC | Space-planning: placement of modules with controlled empty area by single-sequence. | Xuliang Zhang, Yoji Kajitani |
| 2004 | ISCAS | Theory of T-junction floorplans in terms of single-sequence. | Xuliang Zhang, Yoji Kajitani |
| 2003 | ASPDAC | An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. | Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani |
| 2002 | DATE | An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. | Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin |
| 2002 | VLSID | Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. | Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita |
| 2000 | ASPDAC | Self-reforming routing for stochastic search in VLSI interconnection layout. | Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani |
| 2000 | VLSID | Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. | Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake |
| 1999 | ASPDAC | Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. | Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani |
| 1998 | ASPDAC | Air-Pressure-Model-Based Fast Algorithms for General Floorplan. | Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani |
| 1998 | ASPDAC | Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. | Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani |
| 1998 | ICCAD | The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. | Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita |
| 1998 | ICCAD | The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. | Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani |
| 1997 | ASPDAC | A mapping from sequence-pair to rectangular dissection. | Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani |
| 1997 | ASPDAC | Performance and reliability driven clock scheduling of sequential logic circuits. | Atsushi Takahashi, Yoji Kajitani |
| 1997 | ICCAD | Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. | Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani |
| 1996 | DATE | Detailed-Routability of FPGAs with Extremal Switch-Block Structures. | Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani |
| 1996 | ICCAD | Module placement on BSG-structure and IC layout applications. | Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani |
| 1995 | ICCAD | Rectangle-packing-based module placement. | Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani |
| 1994 | ICCAD | Channel-driven global routing with consistent placement (extended abstract). | Shigetoshi Nakatake, Yoji Kajitani |
| 1994 | ISAAC | The Totally-Perfect Bipartite Graph and Its Construction. | Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu |
| 1994 | ISCAS | Design of Optimum Totally Perfect Connection-Blocks of FPGA. | Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu |
| 1994 | WG | New Approximation Results on Graph Matching and related Problems. | Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh |
| 1993 | ISCAS | Optimal single hop multiple bus networks. | Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata |
| 1984 | DAC | The channel expansion problem in layout design. | Rachel R. Chen, Yoji Kajitani |
| 1979 | DAC | The minimum width routing of A 2-row 2-layer polycell-layout. | Tatsuya Kawamoto, Yoji Kajitani |