| 2016 | HCI | Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior. | Chia-Chien Hsu, Yu-Chin Hsu, Ching-Torng Lin |
| 2012 | WSC | Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis. | Yu-Chin Hsu, Rong-Huei Chen, Chih-Ming Fan |
| 2011 | DAC | A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. | Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell |
| 2008 | VTS | A General Failure Candidate Ranking Framework for Silicon Debug. | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
| 2006 | DAC | Visibility enhancement for silicon debug. | Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang |
| 2003 | DAC | Advanced techniques for RTL debugging. | Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai |
| 1999 | DATE | FSMD Functional Partitioning for Low Power. | Enoch Hwang, Frank Vahid, Yu-Chin Hsu |
| 1997 | ASPDAC | On the control-subroutine implementation of subprogram synthesis. | Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee |
| 1996 | DAC | Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. | Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita |
| 1995 | ASPDAC | Synthesis of false loop free circuits. | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang |
| 1993 | ICCAD | High throughput pipelined data path synthesis by conserving the regularity of nested loops. | Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee |
| 1992 | DAC | Zero Skew Clock Net Routing. | Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho |
| 1992 | MICRO | A new approach to schedule operations across nested-ifs and nested-loops. | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang |
| 1991 | DAC | Scheduling for Functional Pipelining and Loop Winding. | Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin |
| 1991 | DAC | An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. | Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu |
| 1991 | ICCAD | Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. | Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu |
| 1990 | DAC | LiB: A Cell Layout Generator. | Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu |
| 1990 | DAC | Data Path Allocation Based on Bipartite Weighted Matching. | Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu |
| 1990 | DAC | Optimum and Heuristic Data Path Scheduling Under Resource Constraints. | Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin |
| 1990 | ICCAD | Rectilinear Steiner Tree Construction by Local and Global Refinement. | Ting-Hai Chao, Yu-Chin Hsu |
| 1990 | ICCAD | Data Path Construction and Refinement. | Fur-Shing Tsai, Yu-Chin Hsu |
| 1989 | ICCAD | An optimal transistor-chaining algorithm for CMOS cell layout. | Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu |
| 1989 | ICCAD | A new integer linear programming formulation for the scheduling problem in data path synthesis. | Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin |
| 1989 | ICCAD | Routing using a pyramid data structure. | Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai |
| 1988 | ICCAD | A detailed router based on simulated evolution. | Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai |