| 2024 | ICCAD | RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. | Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo |
| 2022 | ASPLOS | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. | Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, Andr DeHon |
| 2022 | FPGA | HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. | Yuanlong Xiao, Andr DeHon |
| 2022 | FPL | HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. | Yuanlong Xiao, Aditya Hota, Dongjoon Park, Andr DeHon |
| 2021 | FCCM | HLS-Compatible, Embedded-Processor Stream Links. | Eric Micallef, Yuanlong Xiao, Andr DeHon |
| 2019 | FPGA | Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. | Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai |
| 2018 | FPL | Case for Fast FPGA Compilation Using Partial Reconfiguration. | Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, Andr DeHon |