Yuki Yoshikawa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2009–2013
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | A binding algorithm in high-level synthesis for path delay testability. | Yuki Yoshikawa |
| 2011 | IOLTS | High-level synthesis for multi-cycle transient fault tolerant datapaths. | Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara |
| 2010 | ETS | Hybrid test application in hybrid delay scan design. | Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue |
| 2010 | IOLTS | An FPGA-based fail-soft system with adaptive reconfiguration. | Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue |
| 2009 | ASPDAC | Fast false path identification based on functional unsensitizability using RTL information. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2009 | VTS | A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |