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Yuzheng Ding

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

5

Active years

1992–2005

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

Year	Venue	Title	Authors
2005	FPGA	The effect of post-layout pin permutation on timing.	Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2004	FPGA	Incremental physical resynthesis for timing optimization.	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
1999	FPGA	Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.	Jason Cong, Chang Wu, Yuzheng Ding
1996	FPGA	RASP: A General Logic Synthesis System for SRAM-Based FPGAs.	Jason Cong, John Peck, Yuzheng Ding
1995	FPGA	On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.	Jason Cong, Yuzheng Ding
1993	DAC	On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.	Jason Cong, Yuzheng Ding
1993	ICCAD	Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.	Jason Cong, Yuzheng Ding
1993	WADS	The K-D Heap: An Efficient Multi-dimensional Priority Queue.	Yuzheng Ding, Mark Allen Weiss
1992	ICCAD	An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	Jason Cong, Yuzheng Ding
1992	ICCD	An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.	Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen