| 2021 | DSD | Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. | Jakub Lojda, Richard Panek, Zdenek Kotsek |
| 2021 | DSD | Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. | Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotsek |
| 2020 | DDECS | Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. | Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotsek |
| 2020 | DSD | Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. | Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotsek |
| 2019 | DDECS | Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. | Karel Szurman, Zdenek Kotsek |
| 2019 | DSD | Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. | Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotsek |
| 2019 | DSD | Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. | Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotsek |
| 2018 | DSD | Program Generation Through a Probabilistic Constrained Grammar. | Ondrej Cekan, Jakub Podivinsky, Zdenek Kotsek |
| 2018 | DSD | FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. | Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotsek |
| 2018 | DSD | Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. | Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotsek |
| 2017 | DSD | A Probabilistic Context-Free Grammar Based Random Test Program Generation. | Ondrej Cekan, Zdenek Kotsek |
| 2017 | DSD | Reliability Analysis and Improvement of FPGA-Based Robot Controller. | Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotsek |
| 2016 | DSD | Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. | Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotsek |
| 2016 | DSD | Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis. | Marcela Zacharisov, Michaela Kekelyova-Beleova, Zdenek Kotsek |
| 2015 | DDECS | Application of Evolutionary Algorithms for Regression Suites Optimization. | Michaela Beleova, Zdenek Kotsek, Marcela Simkov, Toma Hruka |
| 2015 | DDECS | Mapping Trained Neural Networks to FPNNs. | Martin Krcma, Jan Kastil, Zdenek Kotsek |
| 2015 | DDECS | FPGA Prototyping and Accelerated Verification of ASIPs. | Jakub Podivinsky, Marcela Simkov, Ondrej Cekan, Zdenek Kotsek |
| 2015 | DSD | Software Fault Tolerance: The Evaluation by Functional Verification. | Ondrej Cekan, Jakub Podivinsky, Zdenek Kotsek |
| 2015 | DSD | Automation and Optimization of Coverage-driven Verification. | Marcela Simkov, Zdenek Kotsek |
| 2014 | DDECS | Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA. | Lukas Miculka, Zdenek Kotsek |
| 2014 | DSD | Automatic Construction of On-line Checking Circuits Based on Finite Automata. | Lucie Matuova, Jan Kastil, Zdenek Kotsek |
| 2014 | DSD | The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. | Jakub Podivinsky, Ondrej Cekan, Marcela Simkov, Zdenek Kotsek |
| 2014 | DSD | State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. | Karel Szurman, Lukas Miculka, Zdenek Kotsek |
| 2013 | DDECS | Analysis and comparison of functional verification and ATPG for testing design reliability. | Marcela Simkov, Zdenek Kotsek, Cristiana Bolchini |
| 2013 | DDECS | Fault tolerant CAN bus control system implemented into FPGA. | Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotsek |
| 2013 | DSD | Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. | Lukas Miculka, Martin Straka, Zdenek Kotsek |
| 2012 | DDECS | Test platform for fault tolerant systems design properties verification. | Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotsek |
| 2012 | DSD | Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. | Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotsek |
| 2011 | DDECS | Decreasing test time by scan chain reorganization. | Pavel Bartos, Zdenek Kotsek, Jan Dohnal |
| 2011 | DDECS | Advanced fault tolerant bus for multicore system implemented in FPGA. | Martin Straka, Jan Kastil, Jaroslav Novotn, Zdenek Kotsek |
| 2011 | DSD | SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | DDECS | Reduction of power dissipation through parallel optimization of test vector and scan register sequences. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2010 | DDECS | Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | DSD | The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2010 | DSD | Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2009 | DSD | High Availability Fault Tolerant Architectures Implemented into FPGAs. | Martin Straka, Zdenek Kotsek |
| 2008 | DDECS | Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. | Luks Starecek, Luks Sekanina, Zdenek Kotsek |
| 2008 | DSD | Power Conscious RTL Test Scheduling. | Jaroslav Skarvada, Zdenek Kotsek, Tomas Herrman |
| 2008 | DSD | Digital Systems Architectures Based on On-line Checkers. | Martin Straka, Zdenek Kotsek, Jan Winter |
| 2007 | DSD | Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. | Jaroslav Skarvada, Tomas Herrman, Zdenek Kotsek |
| 2007 | DSD | Online Protocol Testing for FPGA Based Fault Tolerant Systems. | Jiri Tobola, Zdenek Kotsek, Jan Korenek, Toms Martnek, Martin Straka |
| 2006 | DDECS | FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. | Tomas Pecenka, Zdenek Kotsek, Luks Sekanina |
| 2006 | DDECS | Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. | Luks Sekanina, Luks Starecek, Zdenek Kotsek |
| 2006 | DSD | Testability Estimation Based on Controllability and Observability Parameters. | Tomas Pecenka, Josef Strnadel, Zdenek Kotsek, Luks Sekanina |
| 2005 | DSD | Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. | Josef Strnadel, Zdenek Kotsek |
| 2004 | ISoLA | The Identification of registers in RTL Structures for the Test Application. | Daniel Mika, Josef Strnadel, Zdenek Kotsek |
| 2003 | DSD | Test scheduling for embedded systems. | Zdenek Kotsek, Daniel Mika, Josef Strnadel |
| 2002 | DSD | Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. | Josef Strnadel, Zdenek Kotsek |