| 2026 | ASPDAC | ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework. | Qijun Zhang, Shang Liu, Yao Lu, Mengming Li, Zhiyao Xie |
| 2026 | ASPLOS | PF-LLM: Large Language Model Hinted Hardware Prefetching. | Ceyu Xu, Xiangfeng Sun, Weihang Li, Chen Bai, Bangyan Wang, Mengming Li, Zhiyao Xie, Yuan Xie |
| 2026 | DATE | DAPO: Design Structure-Aware Pass Ordering for HLS via Contrastive and Reinforcement Learning. | Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang |
| 2026 | ISCA | ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses. | Mengming Li, Chenlu Miao, Buqing Xu, Qijun Zhang, Xiangfeng Sun, Ceyu Xu, Yuan Xie, Wenkai Li, Shang Liu, Zhiyao Xie |
| 2026 | ISCA | Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs. | Qijun Zhang, Chen Zhang, Zhuoshan Zhou, Haibo Wang, Zhe Zhou, Zhipeng Tu, Guangyu Sun, Zhiyao Xie, Yijia Diao, Zhigang Ji, Jingwen Leng, Guanghui He, Minyi Guo |
| 2025 | ASPDAC | AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. | Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang |
| 2025 | ASPDAC | PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. | Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2025 | ASPDAC | A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
| 2025 | ASPDAC | Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. | Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie |
| 2025 | ASPDAC | SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. | Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma |
| 2025 | ASPDAC | FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. | Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie |
| 2025 | ASPDAC | Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. | Qijun Zhang, Zhiyao Xie |
| 2025 | DAC | NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. | Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie |
| 2025 | DAC | ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. | Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie |
| 2025 | DAC | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. | Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie |
| 2025 | DAC | ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. | Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan |
| 2025 | DAC | AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling. | Qijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie |
| 2025 | EMNLP | SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models. | Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie |
| 2025 | HPCA | Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency. | Mengming Li, Qijun Zhang, Yongqing Ren, Zhiyao Xie |
| 2025 | ICCAD | GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. | Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie |
| 2025 | ICCAD | HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. | Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie |
| 2025 | ICLR | CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. | Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie |
| 2025 | ISCA | Profile-Guided Temporal Prefetching. | Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie |
| 2024 | ASPDAC | RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. | Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie |
| 2024 | ASPDAC | APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level. | Tao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie |
| 2024 | DAC | Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. | Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang |
| 2024 | DAC | Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. | Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie |
| 2024 | ICCAD | OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. | Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie |
| 2024 | ICCAD | EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen, Hai Helen Li |
| 2024 | ISLPED | Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies. | Yao Lu, Qijun Zhang, Zhiyao Xie |
| 2023 | ASPDAC | Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. | Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2023 | ASPDAC | Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. | Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen |
| 2023 | DAC | PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. | Afzal Ahmad, Zhiyao Xie, Wei Zhang |
| 2023 | DAC | PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. | Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang |
| 2023 | FPGA | FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. | Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang |
| 2023 | ICANN | A Noise Convolution Network for Tampering Detection. | Zhiyao Xie, Xiaochen Yuan, Chan-Tong Lam, Guoheng Huang |
| 2023 | ICANN | RA-Net: A Deep Learning Approach Based on Residual Structure and Attention Mechanism for Image Copy-Move Forgery Detection. | Kaiqi Zhao, Xiaochen Yuan, Zhiyao Xie, Guoheng Huang, Li Feng |
| 2023 | ICCAD | MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. | Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie |
| 2023 | ICCAD | PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. | Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie |
| 2022 | DAC | Towards collaborative intelligence: routability estimation based on decentralized private data. | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen |
| 2022 | ICCAD | Robustify ML-Based Lithography Hotspot Detectors. | Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen |
| 2022 | ICCAD | DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. | Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu |
| 2021 | ASPDAC | Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. | Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen |
| 2021 | ICCAD | Automatic Routability Predictor Development Using Neural Architecture Search. | Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen |
| 2021 | MICRO | APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. | Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das |
| 2020 | ASPDAC | FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. | Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza |
| 2020 | ASPDAC | PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. | Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen |
| 2020 | ICCAD | Routing-Free Crosstalk Prediction. | Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam |
| 2020 | ICCAD | Fast IR Drop Estimation with Machine Learning : Invited Paper. | Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen |
| 2019 | DATE | Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. | Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu |
| 2018 | ICCAD | RouteNet: routability prediction for mixed-size designs using convolutional neural network. | Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu |