Zizhen Liu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
7
Active years
2020–2025
Best venue rank
A*
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. | Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li |
| 2025 | DAC | PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT. | Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | DAC | MOSS: Multi-Modal Representation Learning on Sequential Circuits. | Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li |
| 2025 | DAC | EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components. | Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | DATE | ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. | Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li |
| 2025 | ICCAD | RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. | Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li |
| 2025 | ITC | TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration. | Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li |
| 2025 | VTS | HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. | Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li |
| 2024 | DAC | Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. | Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li |
| 2024 | ICCAD | DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. | Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li |
| 2022 | UAI | SASH: Efficient secure aggregation based on SHPRG for federated learning. | Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li |
| 2020 | VTS | Sequence Triggered Hardware Trojan in Neural Network Accelerator. | Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu |