| 2017 | BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. | Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui |
| 2017 | Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics. | Zuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Yingnan Cui |
| 2017 | On resilient task allocation and scheduling with uncertain quality checkers. | Qian Zhang, Ting Wang, Qiang Xu |
| 2017 | A time domain behavioral model for oscillators considering flicker noise. | Hui Zhang, Bo Wang |
| 2017 | Network flow based cut redistribution and insertion for advanced 1D layout design. | Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng |
| 2017 | Efficient parallel verification of Galois field multipliers. | Cunxi Yu, Maciej J. Ciesielski |
| 2017 | Exploiting accelerated aging effect for on-line configurability and hardware tracking. | Yang You, Jie Gu |
| 2017 | A 686Mbps 1.85mm | Hye-Yeon Yoon, Gwang-Ho Lee, Tae-Hwan Kim |
| 2017 | A 13.56MHz CMOS active diode full-wave rectifier achieving ZVS with voltage-time-conversion delay-locked loop for wireless power transmission. | Keita Yogosawa, Hideki Shinohara, Kousuke Miyaji |
| 2017 | Low-power neuromorphic speech recognition engine with coarse-grain sparsity. | Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo |
| 2017 | ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. | Hiroto Yasuura |
| 2017 | Security analysis of Anti-SAT. | Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran |
| 2017 | A 15 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2017 | Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips. | Xiaokun Yang, Wujie Wen |
| 2017 | An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. | Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
| 2017 | Approximate logic synthesis for FPGA by wire removal and local function change. | Yi Wu, Chuyu Shen, Yi Jia, Weikang Qian |
| 2017 | Design considerations and clinical applications of closed-loop neural disorder control SoCs. | Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw |
| 2017 | Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. | Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong |
| 2017 | A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. | Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta |
| 2017 | Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. | Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai |
| 2017 | Temperature-aware data allocation strategy for 3D charge-trap flash memory. | Yi Wang, Mingxu Zhang, Jing Yang |
| 2017 | Towards scalable and efficient GPU-enabled slicing acceleration in continuous 3D printing. | Aosen Wang, Chi Zhou, Zhanpeng Jin, Wenyao Xu |
| 2017 | Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses. | Yandan Wang, Wei Wen, Linghao Song, Hai Helen Li |
| 2017 | CNN-based object detection solutions for embedded heterogeneous multicore SoCs. | Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li |
| 2017 | An effective legalization algorithm for mixed-cell-height standard cells. | Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan |