| 2023 | ASPDAC | Static Probability Analysis Guided RTL Hardware Trojan Test Generation. | Haoyi Wang, Qiang Zhou, Yici Cai |
| 2023 | ASPDAC | Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. | Jianwang Zhai, Yici Cai, Bei Yu |
| 2022 | ICPR | TransMarker: A Pure Vision Transformer for Facial Landmark Detection. | Wenyan Wu, Yici Cai, Qiang Zhou |
| 2021 | ICCAD | McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. | Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu |
| 2021 | ISCAS | An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. | Lin Li, Yici Cai, Qiang Zhou |
| 2021 | ISCAS | A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. | Jing Wang, Yici Cai, Qiang Zhou |
| 2019 | ISCAS | Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. | Jing Wang, Yici Cai, Ming Yan, Qiang Zhou |
| 2018 | ASPDAC | HLIFT: A high-level information flow tracking method for detecting hardware Trojans. | Chenguang Wang, Yici Cai, Qiang Zhou |
| 2018 | ASPDAC | ASAX: Automatic security assertion extraction for detecting Hardware Trojans. | Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang |
| 2018 | ASPDAC | A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. | Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu |
| 2018 | CVPR | Look at Boundary: A Boundary-Aware Face Alignment Algorithm. | Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou |
| 2018 | ICCAD | Electromagnetic equalizer: an active countermeasure against EM side-channel attack. | Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou |
| 2017 | ASPDAC | Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. | Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai |
| 2017 | BigData | TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy. | Yunxing Xin, Yongqiang Chen, Li Jin, Yici Cai, Ling Feng |
| 2017 | DATE | Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks. | Xiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang |
| 2017 | ICCD | Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. | Chenguang Wang, Yici Cai, Qiang Zhou |
| 2017 | ICCD | Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. | Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang |
| 2017 | ISCAS | Cell spreading optimization for force-directed global placers. | Xueyan Wang, Yici Cai, Qiang Zhou |
| 2016 | ASPDAC | Sequence-pair-based placement and routing for flow-based microfluidic biochips. | Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai |
| 2016 | ICCAD | Control-fluidic CoDesign for paper-based digital microfluidic biochips. | Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai |
| 2016 | ISCAS | An efficient framework for configurable RO PUF. | Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu |
| 2016 | ISCAS | Is the Secure IC camouflaging really secure? | Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu |
| 2015 | ASPDAC | Early stage real-time SoC power estimation using RTL instrumentation. | Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai |
| 2015 | DAC | PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. | Hailong Yao, Tsung-Yi Ho, Yici Cai |
| 2014 | ASPDAC | VFGR: A very fast parallel global router with accurate congestion modeling. | Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen |
| 2014 | ASPDAC | Time-domain performance bound analysis for analog and interconnect circuits considering process variations. | Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang |
| 2014 | ASPDAC | Fast vectorless power grid verification using maximum voltage drop location estimation. | Wei Zhao, Yici Cai, Jianlei Yang |
| 2014 | DAC | Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. | Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai |
| 2014 | ICCAD | MCFRoute: a detailed router based on multi-commodity flow method. | Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li |
| 2014 | ICCD | Accurate prediction of detailed routing congestion using supervised data learning. | Zhongdong Qi, Yici Cai, Qiang Zhou |
| 2014 | ISCAS | A register clustering algorithm for low power clock tree synthesis. | Chao Deng, Yici Cai, Qiang Zhou |
| 2013 | ASPDAC | Performance bound and yield analysis for analog circuits under process variations. | Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai |
| 2013 | ASPDAC | A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. | Wei Zhao, Yici Cai, Jianlei Yang |
| 2013 | ICCD | Selected inversion for vectorless power grid verification by exploiting locality. | Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao |
| 2012 | ASPDAC | Thermal-aware power network design for IR drop reduction in 3D ICs. | Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie |
| 2012 | ASPDAC | LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. | Hailong Yao, Yici Cai, Qiang Gao |
| 2012 | ICCAD | PowerRush : Efficient transient simulation for power grid analysis. | Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou |
| 2011 | CSCWD | A fast recursive detailed routing algorithm for hierarchical FPGAs. | Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai |
| 2011 | ICCAD | Fast poisson solver preconditioned method for robust power grid analysis. | Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi |
| 2011 | ICCAD | PowerRush: A linear simulator for power grid. | Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou |
| 2010 | ASPDAC | Efficient power grid integrity analysis using on-the-fly error check and reduction. | Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai |
| 2010 | ASPDAC | Efficient model reduction of interconnects via double gramians approximation. | Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai |
| 2010 | CSCWD | An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. | Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian |
| 2010 | DATE | SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. | Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu |
| 2010 | ISLPED | Analog circuit shielding routing algorithm based on net classification. | Qiang Gao, Yin Shen, Yici Cai, Hailong Yao |
| 2009 | ASPDAC | Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. | Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
| 2009 | DAC | GPU friendly fast Poisson solver for structured power grid network analysis. | Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang |
| 2009 | DATE | An efficient decoupling capacitance optimization using piecewise polynomial models. | Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles |
| 2009 | DDECS | Fast congestion-aware timing-driven placement for island FPGA. | Jinpeng Zhao, Qiang Zhou, Yici Cai |
| 2009 | ICCAD | Decoupling capacitance efficient placement for reducing transient power supply noise. | Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia |
| 2008 | ASPDAC | Vertical via design techniques for multi-layered P/G networks. | Shuai Li, Jin Shi, Yici Cai, Xianlong Hong |
| 2008 | ASPDAC | Heuristic power/ground network and floorplan co-design method. | Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong |
| 2008 | ASPDAC | Low power clock buffer planning methodology in F-D placement for large scale circuit design. | Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian |
| 2008 | FPL | MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. | Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong |
| 2008 | ICCD | Gate planning during placement for gated clock network. | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
| 2008 | ISCAS | Leakage power optimization for clock network using dual-Vth technology. | Weixiang Shen, Yici Cai, Xianlong Hong |
| 2007 | ASPDAC | Logic and Layout Aware Voltage Island Generation for Low Power Design. | Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2007 | ASPDAC | Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. | Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan |
| 2007 | ASPDAC | Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang |
| 2007 | DATE | Statistical model order reduction for interconnect circuits considering spatial correlations. | Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
| 2007 | ICCAD | Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. | Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong |
| 2007 | ISCAS | Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. | Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai |
| 2007 | ISCAS | Effective Acceleration of Iterative Slack Distribution Process. | Xinjie Wei, Yici Cai, Xianlong Hong |
| 2006 | ASPDAC | Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. | Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2006 | ASPDAC | Efficient early stage resonance estimation techniques for C4 package. | Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong |
| 2006 | ICCAD | Efficient process-hotspot detection using range pattern matching. | Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai |
| 2006 | ISCAS | A novel technique integrating buffer insertion into timing driven placement. | Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang |
| 2006 | ISCAS | High performance clock routing in X-architecture. | Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu |
| 2006 | ISCAS | Performance and power aware buffered tree construction. | Yibo Wang, Yici Cai, Xianlong Hong |
| 2006 | ISCAS | Congestion-driven W-shape multilevel full-chip routing framework. | Hailong Yao, Yici Cai, Xianlong Hong |
| 2006 | ISCAS | A novel low-power physical design methodology for MTCMOS. | Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2005 | ASPDAC | Relaxed hierarchical power/ground grid analysis. | Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu |
| 2005 | ASPDAC | VLSI on-chip power/ground network optimization considering decap leakage currents. | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
| 2005 | ASPDAC | Clock network minimization methodology based on incremental placement. | Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu |
| 2005 | ASPDAC | Register placement for low power clock network. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | ASPDAC | Analysis of buffered hybrid structured clock networks. | Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
| 2005 | DAC | Partitioning-based approach to fast on-chip decap budgeting and minimization. | Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong |
| 2005 | DAC | Navigating registers in placement for clock network minimization. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | ICNC | A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. | Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong |
| 2005 | ISCAS | Integrated routing resource assignment for RLC crosstalk minimization. | Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong |
| 2005 | ISCAS | A global interconnect optimization algorithm under accurate delay model using solution space smoothing. | Yici Cai, Yibo Wang, Xianlong Hong |
| 2005 | ISCAS | A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani |
| 2005 | ISCAS | Zero skew clock routing with tree topology construction using simulated annealing method. | Xinjie Wei, Yici Cai, Xianlong Hong |
| 2005 | ISCAS | An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. | Yiqian Zhang, Xianlong Hong, Yici Cai |
| 2005 | VLSID | A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. | Yibo Wang, Yici Cai, Xianlong Hong |
| 2004 | ASPDAC | A buffer planning algorithm with congestion optimization. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ASPDAC | A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
| 2004 | ASPDAC | Buffer allocation algorithm with consideration of routing congestion. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2004 | ICCD | A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. | Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan |
| 2004 | ISCAS | Layer assignment algorithm for RLC crosstalk minimization. | Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong |
| 2004 | ISCAS | Algorithm for yield driven correction of layout. | Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou |
| 2004 | ISCAS | Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. | Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu |
| 2004 | ISCAS | Crosstalk driven routing resource assignment. | Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai |
| 2004 | ISCAS | Shielding area optimization under the solution of interconnect crosstalk. | Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong |
| 2004 | ISCAS | Quick and effective buffered legitimate skew clock routing. | Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong |
| 2003 | ASPDAC | A buffer planning algorithm based on dead space redistribution. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | A path-based timing-driven quadratic placement algorithm. | Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai |
| 2003 | ASPDAC | UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. | Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu |
| 2003 | ASPDAC | A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. | Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu |
| 2003 | DAC | Dynamic global buffer planning optimization based on detail block locating and congestion analysis. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Evaluating a bounded slice-line grid assignment in O(nlogn) time. | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2003 | ISCAS | Combining clustering and partitioning in quadratic placement. | Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai |
| 2003 | ISCAS | Arbitrary convex and concave rectilinear block packing based on corner block list. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu |
| 2002 | ISCAS | A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. | Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu |
| 2002 | VLSID | Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2002 | VLSID | An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. | Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu |
| 2001 | ASPDAC | A new congestion-driven placement algorithm based on cell inflation. | Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao |
| 2001 | ASPDAC | VLSI floorplanning with boundary constraints based on corner block list. | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | DAC | Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
| 2001 | ICCAD | Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. | Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai |
| 2000 | ASPDAC | Area routing oriented hierarchical corner stitching with partial bin. | Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong |
| 2000 | ASPDAC | MMP: a novel placement algorithm for combined macro block and standard cell layout design. | Hong Yu, Xianlong Hong, Yici Cai |
| 2000 | ICCAD | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
| 1999 | ASPDAC | A New Global Routing Algorithm Independent Of Net Ordering. | Haiyun Bao, Xianlong Hong, Yici Cai |
| 1999 | ASPDAC | A Timing-Driven Block Placer Based on Sequence Pair Model. | Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai |