| 2014 | VFGR: A very fast parallel global router with accurate congestion modeling. | Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen |
| 2014 | A comprehensive and accurate latency model for Network-on-Chip performance analysis. | Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu |
| 2014 | Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. | Gregory di Pendina, Kotb Jabeur, Guillaume Prenat |
| 2014 | Array scalarization in high level synthesis. | Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan |
| 2014 | ArISE: Aging-aware instruction set encoding for lifetime improvement. | Fabian Oboril, Mehdi Baradaran Tahoori |
| 2014 | Efficient synthesis of quantum circuits implementing clifford group operations. | Philipp Niemann, Robert Wille, Rolf Drechsler |
| 2014 | Applying VLSI EDA to energy distribution system design. | Sani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri |
| 2014 | Normally-off computing project: Challenges and opportunities. | Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa |
| 2014 | Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. | Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo |
| 2014 | A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise. | Takashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara, Makoto Igarashi, Seiji Samukawa |
| 2014 | Rethinking error injection for effective resilience. | Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham |
| 2014 | Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. | Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li |
| 2014 | DRuiD: Designing reconfigurable architectures with decision-making support. | Giovanni Mariani, Gianluca Palermo, Roel Meeuws, Vlad Mihai Sima, Cristina Silvano, Koen Bertels |
| 2014 | Prefetching techniques for STT-RAM based last-level cache in CMP systems. | Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen |
| 2014 | Quantum key distribution with integrated optics. | Mirko Lobino, Pei Zhang, Enrique Martin-Lopez, Richard W. Nock, Damien Bonneau, Hongwei Li, Antti O. Niskanen, Jeremy Lloyd O'Brien, Anthony Laing, Kanin Aungskunsiri, Joachim Wabnig, Jack Munns, Pisu Jiang, John G. Rarity, Mark G. Thompson |
| 2014 | Training itself: Mixed-signal training acceleration for memristor-based neural network. | Boxun Li, Yuzhi Wang, Yu Wang, Yiran Chen, Huazhong Yang |
| 2014 | STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. | Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, Yiran Chen |
| 2014 | QED post-silicon validation and debug: Frequently asked questions. | David Lin, Subhasish Mitra |
| 2014 | Analytical placement of mixed-size circuits for better detailed-routability. | Shuai Li, Cheng-Kok Koh |
| 2014 | Multi-mode trace signal selection for post-silicon debug. | Min Li, Azadeh Davoodi |
| 2014 | Synthesis of power- and area-efficient binary machines for incompletely specified sequences. | Nan Li, Elena Dubrova |
| 2014 | A hybrid random walk algorithm for 3-D thermal analysis of integrated circuits. | Yuan Liang, Wenjian Yu, Haifeng Qian |
| 2014 | Fast large-scale optimal power flow analysis for smart grid through network reduction. | Yi Liang, Deming Chen |
| 2014 | Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. | Anders Lansner, Ahmed Hemani, Nasim Farahini |
| 2014 | Adaptive interpolation-based model checking. | Chien-Yu Lai, Cheng-Yin Wu, Chung-Yang (Ric) Huang |