| 2012 | Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties. | Yang Song, Guoyong Shi |
| 2012 | Synthesis of reversible circuits with minimal lines for large functions. | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| 2012 | Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs. | Rohit Sinha, Aayush Prakash, Hiren D. Patel |
| 2012 | Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables. | Yang Shang, Wei Fei, Hao Yu |
| 2012 | Linear decomposition of index generation functions. | Tsutomu Sasao |
| 2012 | Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. | Omid Sarbishei, Katarzyna Radecka |
| 2012 | A reconfigurable accelerator for neuromorphic object recognition. | Jagdish Sabarad, Srinidhi Kestur, Mi Sun Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla |
| 2012 | Low-cost control flow error protection by exploiting available redundancies in the pipeline. | Mohammad Abdur Rouf, Soontae Kim |
| 2012 | Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. | Sascha Roloff, Frank Hannig, Jrgen Teich |
| 2012 | A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k2k H.264/AVC video encoder. | Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng |
| 2012 | RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware. | Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jrg Henkel |
| 2012 | Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. | Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman |
| 2012 | Automatic timing granularity adjustment for host-compiled software simulation. | Parisa Razaghi, Andreas Gerstlauer |
| 2012 | An application classification guided cache tuning heuristic for multi-core architectures. | Marisha Rawlins, Ann Gordon-Ross |
| 2012 | ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures. | Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2012 | Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. | Hctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose |
| 2012 | Invasive Computing for robotic vision. | Johny Paul, Walter Stechele, Manfred Krhnert, Tamim Asfour, Rdiger Dillmann |
| 2012 | A reconfigurable platform for the design and verification of domain-specific accelerators. | Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan |
| 2012 | Design for manufacturability and reliability for TSV-based 3D ICs. | David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang |
| 2012 | Detection and diagnosis of faulty quantum circuits. | Alexandru Paler, Ilia Polian, John P. Hayes |
| 2012 | Accelerated processing and the Fusion System Architecture. | Mike O'Connor |
| 2012 | Low power memristor-based ReRAM design with Error Correcting Code. | Dimin Niu, Yang Xiao, Yuan Xie |
| 2012 | A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. | Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi |
| 2012 | Optimizing test-generation to the execution platform. | Amir Nahir, Avi Ziv, Subrat Panda |
| 2012 | JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency. | Muhammad Nadeem, Morteza Biglari-Abhari, Zoran Salcic |