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IEEE/ACM International Symposium on Low Power Electronics and Design

ISLPED

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering · Applied Computing

Papers indexed

2,128

1995–2026

Papers per year

199595 peak2026

ISLPED papers

2,128 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008Lazy instruction scheduling: keeping performance, reducing power.Ali Mahjur, Mahmud Taghizadeh, Amir-Hossein Jahangir
2008Variability of flip-flop timing at sub-threshold voltages.Niklas Lotze, Maurits Ortmanns, Yiannos Manoli
2008A probabilistic technique for full-chip leakage estimation.Shaobo Liu, Qinru Qiu, Qing Wu
2008Single stage static level shifter design for subthreshold to I/O voltage conversion.Yu-Shiang Lin, Dennis Sylvester
2008A 1-V piecewise curvature-corrected CMOS bandgap reference.Jing-hu Li, Yu-nan Fu, Yong-sheng Wang
2008Entry control in network-on-chip for memory power reduction.Dongwook Lee, Sungjoo Yoo, Kiyoung Choi
2008Energy conservation by adaptive feature loading for mobile content-based image retrieval.Karthik Kumar, Yamini Nimmagadda, Yu-Ju Hong, Yung-Hsiang Lu
2008Extending the lifetime of media recorders constrained by battery and flash memory size.Younghyun Kim, Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Nam Ik Cho
2008A secure and low-energy logic style using charge recovery approach.Mehrdad Khatir, Amir Moradi, Alireza Ejlali, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh
2008SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
2008Word-interleaved cache: an energy efficient data cache architecture.T. Venkata Kalyan, Madhu Mutyam
2008Frequency planning for multi-core processors under thermal constraints.Michael Kadin, Sherief Reda
2008System implications of integrated photonics.Norman P. Jouppi
2008A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes.Jie Jin, Chi-Ying Tsui
2008EnhancingDong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim
2008A multi-story power delivery technique for 3D integrated circuits.Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim
2008SOC designs in the energy conscious era.Srikanth Jadcherla
2008An expected-utility based approach to variation aware VLSI optimization under scarce information.Upavan Gupta, Nagarajan Ranganathan
2008Energy harvesting photodiodes with integrated 2D diffractive storage capacitance.Nathaniel J. Guilar, Erin G. Fong, Travis Kleeburg, Diego R. Yankelevich, Rajeevan Amirtharajah
2008Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation.Maziar Goudarzi, Tohru Ishihara
2008Thread fusion.Jos Gonzlez, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan N. Rakvic, Antonio Gonzlez
2008OSwaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy
2008Design of dual threshold voltages asynchronous circuits.Behnam Ghavami, Hossein Pedram
2008A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops.Mohammad Ghasemazar, Behnam Amelifard, Massoud Pedram
2008Innovations to extend CMOS nano-transistors to the limit.Tahir Ghani
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