| 2003 | Reducing power density through activity migration. | Seongmoo Heo, Kenneth C. Barr, Krste Asanovic |
| 2003 | A systems approach to molecular electronics. | James R. Heath |
| 2003 | Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology. | Drew Guckenberger, Kevin T. Kornegay |
| 2003 | Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. | Flavius Gruian, Krzysztof Kuchcinski |
| 2003 | ILP-based optimization of sequential circuits for low power. | Feng Gao, John P. Hayes |
| 2003 | Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converter. | Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee |
| 2003 | Voltage scheduling under unpredictabilities: a risk management paradigm. | Azadeh Davoodi, Ankur Srivastava |
| 2003 | Effective graph theoretic techniques for the generalized low power binding problem. | Azadeh Davoodi, Ankur Srivastava |
| 2003 | New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. | Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown |
| 2003 | Energy recovery clocking scheme and flip-flops for ultra low-energy applications. | Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2003 | Reducing translation lookaside buffer active power. | Lawrence T. Clark, Byungwoo Choi, Michael W. Wilkerson |
| 2003 | B#: a battery emulator and power profiling instrument. | Pai H. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu |
| 2003 | Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. | Woo Young Choi, Jong Duk Lee, Byung-Gook Park |
| 2003 | LPBP: low-power basis profile of the Java 2 Micro Edition. | Inseok Choi, Hyung Soo Kim, Heonshik Shin, Naehyuck Chang |
| 2003 | UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. | Kyu-won Choi, Abhijit Chatterjee |
| 2003 | Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
| 2003 | Leakage power modeling and optimization in interconnection networks. | Xuning Chen, Li-Shiuan Peh |
| 2003 | Low-power high-level synthesis for FPGA architectures. | Deming Chen, Jason Cong, Yiping Fan |
| 2003 | Branch prediction on demand: an energy-efficient solution. | Daniel Chaver, Luis Piuel, Manuel Prieto, Francisco Tirado, Michael C. Huang |
| 2003 | Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. | Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar |
| 2003 | A power-aware SWDR cell for reducing cache write power. | Yen-Jen Chang, Chia-Lin Yang, Feipei Lai |
| 2003 | A semi-custom voltage-island technique and its application to high-speed serial links. | Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman |
| 2003 | Design methodology for fine-grained leakage control in MTCMOS. | Benton H. Calhoun, Frank Honor, Anantha P. Chandrakasan |
| 2003 | ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. | Kavel M. Byksahin, Priyadarsan Patra, Farid N. Najm |
| 2003 | Energy-efficient data scrambling on memory-processor interfaces. | Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino |