| 1996 | A low power high performance switched-current multiplier. | Domine Leenaerts, G. H. M. Joordens, Johannes A. Hegt |
| 1996 | Transition reduction in carry-save adder trees. | Patrik Larsson, Chris J. Nicol |
| 1996 | High-level power estimation. | Paul E. Landman |
| 1996 | Substrate noise influence on circuit performance in variable threshold-voltage scheme. | Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai |
| 1996 | Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. | Ram K. Krishnamurthy, Ihor Lys, L. Richard Carley |
| 1996 | Interlaced accumulation programming for low power DSP. | Hirotsugu Kojima, Avadhani Shridhar |
| 1996 | Design techniques for high performance, energy efficient control logic. | Uming Ko, Anthony M. Hill, Poras T. Balsara |
| 1996 | What is the state of the art in commercial EDA tools for low power? | Kurt Keutzer, Olivier Coudert, Ramsey W. Haddad |
| 1996 | Simulation based architectural power estimation for PLA-based controllers. | Srinivas Katkoori, Ranga Vemuri |
| 1996 | Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. | Tohru Ishihara, Hiroto Yasuura |
| 1996 | A novel methodology for transistor-level power estimation. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | A 200 A, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm. | Qiuting Huang, Philipp Basedau |
| 1996 | Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. | Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki |
| 1996 | Micro power "relative precision" 13 bits cyclic RSD A/D converter. | Alexandre Heubi, Peter Balsiger, Fausto Pellandini |
| 1996 | Implementation of a micro power 15-bit "floating-point" A/D converter. | L. Grisoni, Alexandre Heubi, Peter Balsiger, Fausto Pellandini |
| 1996 | Low-power adaptive filter architectures via strength reduction. | Manish Goel, Naresh R. Shanbhag |
| 1996 | Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management. | Rafael Fried, Ziv Azmanov |
| 1996 | Comparison of high speed voltage-scaled conventional and adiabatic circuits. | David J. Frank |
| 1996 | Design of a programmable temperature monitoring device for tagging small fish. | Godi Fischer, James C. Daly, Chun Yang, Conrad W. Recksiek, Kevin D. Friedland |
| 1996 | The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. | M. Eisele, Jrg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf |
| 1996 | The design of a high performance low power microprocessor. | Dan Dobberpuhl |
| 1996 | A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). | Vivek De, James D. Meindl |
| 1996 | Integrated resynthesis for low power. | Olivier Coudert, Ramsey W. Haddad |
| 1996 | Simultaneous buffer and wire sizing for performance and power optimization. | Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung |
| 1996 | Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. | Kai Chen, Yuhua Cheng, Chenming Hu |