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IEEE/ACM International Symposium on Low Power Electronics and Design

ISLPED

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering · Applied Computing

Papers indexed

2,128

1995–2026

Papers per year

199595 peak2026

ISLPED papers

2,128 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1996An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits.Amitava Chatterjee, Mahalingam Nandakumar, Ih-Chin Chen
1996Energy minimization using multiple supply voltages.Jui-Ming Chang, Massoud Pedram
1996Data driven signal processing: an approach for energy efficient computing.Anantha P. Chandrakasan, Vadim Gutnik, Thucydides Xanthopoulos
1996Fabrication and performance of mesa interconnect.L. Richard Carley, David F. Guillou, Suresh Santhanam
1996Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel).James Burr, Laszlo Gal, Ramsey W. Haddad, Jan M. Rabaey, Bruce Wooley
1996Low power systems for wireless microsensors.K. Bult, Amit Burstein, D. Chang, Michael J. Dong, M. Fielding, E. Kruglick, J. Ho, F. Lin, Tsung-Hsien, William J. Kaiser, H. Marcy, R. Mukai, Phyllis R. Nelson, F. Newburg, Kristofer S. J. Pister, Gregory J. Pottie, Henry Sanchez, Oscar M. Stafsudd, K. B. Tan, S. Xue, J. Yao
1996Gate-level current waveform simulation of CMOS integrated circuits.Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Ricc
1996Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices.Labros Bisdounis, Odysseas G. Koufopavlou, Spiridon Nikolaidis
1996Circuit techniques for low-power CMOS GSI.Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
1996Practical performance/power alternatives within an existing CMOS technology generation.Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak
1996Symbolic computation of logic implications for technology-dependent low-power synthesis.R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
1996Energy-recovery CMOS for highly pipelined DSP designs.William C. Athas, Weichuan Liu, Lars J. Svensson
1996Power comparisons for barrel shifters.Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
1995Transforming set data types to power optimal data structures.Sven Wuytack, Francky Catthoor, Hugo De Man
1995Re-encoding for low power state assignment of FSMs.Vamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal
1995Clustered voltage scaling technique for low-power design.Kimiyoshi Usami, Mark Horowitz
1995Explicit evaluation of short circuit power dissipation for CMOS logic structures.S. Turgis, Nadine Azmard, Daniel Auvergne
1995Guarded evaluation: pushing power management to logic synthesis/design.Vivek Tiwari, Sharad Malik, Pranav Ashar
1995Power and area optimization by reorganizing CMOS complex gate circuits.M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto
1995Cache design trade-offs for power and performance optimization: a case study.Ching-Long Su, Alvin M. Despain
1995Variable voltage scheduling.Salil Raje, Majid Sarrafzadeh
1995Logic design for low-voltage/low-power CMOS circuits.Christian Piguet, Jean-Marc Masgonty, Vincent von Kaenel, Thierry Schneider
1995CMOS dynamic power estimation based on collapsible current source transistor modeling.Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
1995A multiple clocking scheme for low power RTL design.Christos A. Papachristou, Mark Spining, Mehrdad Nourani
1995Reducing the frequency of tag compares for low power I-cache design.Ramesh Panwar, David A. Rennels
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