| 1995 | Towards a high-level power estimation capability. | Farid N. Najm |
| 1995 | Unifying carry-sum and signed-digital number representations for low power. | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
| 1995 | High-level synthesis techniques for reducing the activity of functional units. | Enric Musoll, Jordi Cortadella |
| 1995 | Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. | Jos Monteiro, Srinivas Devadas |
| 1995 | Information theoretic measures of energy consumption at register transfer level. | Diana Marculescu, Radu Marculescu, Massoud Pedram |
| 1995 | An estimation technique to guide low power resynthesis algorithms. | Christopher K. Lennard, A. Richard Newton |
| 1995 | Activity-sensitive architectural power analysis for the control path. | Paul E. Landman, Jan M. Rabaey |
| 1995 | 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. | Alan Kramer, John S. Denker, B. Flower, J. Moroney |
| 1995 | Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors. | Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, Marco Sabatini, P. Zabberoni |
| 1995 | Energy optimization of multi-level processor cache architectures. | Uming Ko, Poras T. Balsara, Ashwini K. Nanda |
| 1995 | Charge recovery on a databus. | Kei-Yong Khoo, Alan N. Willson Jr. |
| 1995 | The design and implementation of PowerMill. | Charlie X. Huang, Bill Zhang, An-Chang Deng, Burkhard Swirski |
| 1995 | Determining accuracy bounds for simulation-based switching activity estimation. | Anthony M. Hill, Sung-Mo Kang |
| 1995 | Transistor reordering for low power CMOS gates using an SP-BDD representation. | Alexey Glebov, David T. Blaauw, Larry G. Jones |
| 1995 | Low power and EMI, high frequency, crystal oscillator. | Rafael Fried, Reuven Holzer |
| 1995 | Electroid-oriented adiabatic switching circuits. | David J. Frank, Paul M. Solomon |
| 1995 | Analysis of glitch power dissipation in CMOS ICs. | Michele Favalli, Luca Benini |
| 1995 | The CAD challenges of designing low power, high performance VLSI system. | Walter Davis |
| 1995 | Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. | Aurobindo Dasgupta, Ramesh Karri |
| 1995 | Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers. | Anthony Correale Jr. |
| 1995 | Optimization of power dissipation and skew sensitivity in clock buffer synthesis. | Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1995 | Low delay-power product CMOS design using one-hot residue coding. | William A. Chren Jr. |
| 1995 | Techniques for fast circuit simulation applied to power estimation of CMOS circuits. | Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh |
| 1995 | Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
| 1995 | High-throughput and low-power DSP using clocked-CMOS circuitry. | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |