Skip to content

International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2020Uncovering Hidden Instructions in Armv8-A Implementations.Fredrik Strupe, Rakesh Kumar
2020MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product.Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang
2020VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration.Zhuoran Song, Feiyang Wu, Xueyuan Liu, Jing Ke, Naifeng Jing, Xiaoyao Liang
2020Draco: Architectural and Operating System Support for System Call Security.Dimitrios Skarlatos, Qingrong Chen, Jianyan Chen, Tianyin Xu, Josep Torrellas
2020Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks.Gil Shomron, Uri C. Weiser
2020Jumanji: The Case for Dynamic NUCA in the Datacenter.Brian C. Schwedock, Nathan Beckmann
2020Speculative Enforcement of Store Atomicity.Alberto Ros, Stefanos Kaxiras
2020gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling.Samuel Rogers, Joshua Slycord, Mohammadreza Baharani, Hamed Tabkhi
2020MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications.Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020DiffTune: Optimizing CPU Simulator Parameters with Learned Differentiable Surrogates.Alex Renda, Yishen Chen, Charith Mendis, Michael Carbin
2020Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration.Akshay Krishna Ramanathan, Gurpreet S. Kalsi, Srivatsa Srinivasa, Tarun Makesh Chandran, Kamlesh R. Pillai, Om Ji Omer, Vijaykrishnan Narayanan, Sreenivas Subramoney
2020GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing.Shafiur Rahman, Nael B. Abu-Ghazaleh, Rajiv Gupta
2020ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation.Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee
2020Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics.Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, Onur Mutlu
2020Graphene: Strong yet Lightweight Row Hammer Protection.Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, Jae W. Lee
2020TrainBox: An Extreme-Scale Neural Network Training Server Architecture by Systematically Balancing Operations.Pyeongsu Park, Heetaek Jeong, Jangwoo Kim
2020Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism.Quan M. Nguyen, Daniel Snchez
2020DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms.Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2020Printed Machine Learning Classifiers.Muhammad Husnain Mubarik, Dennis D. Weller, Nathaniel Bleier, Matthew Tomei, Jasmin Aghassi-Hagmann, Mehdi B. Tahoori, Rakesh Kumar
2020FPGA Bitstream Modification with Interconnect in Mind.Michail Moraitis, Elena Dubrova
2020TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks.Huiyu Mo, Leibo Liu, Wenjing Hu, Wenping Zhu, Qiang Li, Ang Li, Shouyi Yin, Jian Chen, Xiaowei Jiang, Shaojun Wei
2020HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes.Amirhossein Mirhosseini, Hossein Golestani, Thomas F. Wenisch
2020PerpLE: Improving the Speed and Effectiveness of Memory Consistency Testing.Themis Melissaris, Markos Markakis, Kelly A. Shaw, Margaret Martonosi
2020Implementing the Draft RISC-V Scalar Cryptography Extensions.Ben Marshall, Daniel Page, Thinh Hung Pham
2020Position Paper: Defending Direct Memory Access with CHERI Capabilities.A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
551575 of 2,401← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.