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International Symposium on Microarchitecture

MICRO

A*

CORE rank

CORE rank (raw)

A*

Acceptance rate

21.0% (2023)

Fields of research

Computer Systems Engineering

Papers indexed

2,401

1972–2025

Papers per year

1972123 peak2025

MICRO papers

2,401 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2005A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation.Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross
2005Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham
2005Exploiting Vector Parallelism in Software Pipelined Loops.Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe
2005Thermal Management of On-Chip Caches Through Power Density Minimization.Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
2005Efficient Use of Invisible Registers in Thumb Code.Arvind Krishnaswamy, Rajiv Gupta
2005Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors.Meyrem Kirman, Nevin Kirman, Jos F. Martnez
2005Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
2005The Cell Processor Architecture.James A. Kahle
2005The Future Evolution of High-Performance Microprocessors.Norman P. Jouppi
2005Improving Region Selection in Dynamic Optimization Systems.David Hiniker, Kim M. Hazelwood, Michael D. Smith
2005Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.Stephen Hines, Gary S. Tyson, David B. Whalley
2005Stream Programming on General-Purpose Processors.Jayanth Gummaraju, Mendel Rosenblum
2005Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System.Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
2005Store Memory-Level Parallelism Optimizations for Commercial Applications.Yuan Chou, Lawrence Spracklen, Santosh G. Abraham
2005A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.Fred A. Bower, Daniel J. Sorin, Sule Ozev
2005Continuous Path and Edge Profiling.Michael D. Bond, Kathryn S. McKinley
2005uComplexity: Estimating Processor Design Effort.Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
2005"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense.Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu
2004AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants.Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas
2004Whole Execution Traces.Xiangyu Zhang, Rajiv Gupta
2004RIFLE: An Architectural Framework for User-Centric Information-Flow Security.Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August
2004Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
2004Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow.Nathan Tuck, Brad Calder, George Varghese
2004Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation.Gurindar S. Sohi
2004Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures.Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
1,5011,525 of 2,401← PreviousNext →

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