A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
Browse the full ASPDAC paper archive.
Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
Browse the full ASPDAC paper archive.