A 64-MHz∼640-MHz 64-phase clock generator.
Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
Browse the full DDECS paper archive.
Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
Browse the full DDECS paper archive.