| 2025 | ISCAS | A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces. | Yi-Ting Yang, Hao-Chiao Hong, Kuo-Hsing Cheng |
| 2019 | DDECS | A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System. | Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng |
| 2018 | ISCAS | A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. | Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng |
| 2016 | DDECS | Gm-C filter with automatic calibration scheme. | Hong-Yi Huang, Kun-Yuan Chen, Jiahao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng |
| 2016 | DDECS | Low-voltage indoor energy harvesting using photovoltaic cell. | Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng |
| 2016 | DDECS | A chaotically injected timing technique for ring-based oscillators. | Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang |
| 2015 | DDECS | PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. | Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou |
| 2015 | DDECS | A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. | Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang |
| 2014 | DDECS | A 64-MHz∼640-MHz 64-phase clock generator. | Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng |
| 2014 | DDECS | A low supply voltage synchronous mirror delay with quadrature phase output. | Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang |
| 2013 | DDECS | External capacitorless low dropout linear regulator using cascode structure. | Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng |
| 2013 | DDECS | Indoor energy harvesting using photovoltaic cell for battery recharging. | Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng |
| 2013 | DDECS | A low jitter delay-locked-loop applied for DDR4. | Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang |
| 2012 | DDECS | Auto-calibration techniques in built-in jitter measurement circuit. | Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng |
| 2012 | ISCAS | A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-m CMOS technology. | Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng |
| 2011 | ISCAS | All digital phase-locked loop using active inductor oscillator and novel locking algorithm. | Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo |
| 2010 | DDECS | A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. | Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang |
| 2009 | DDECS | 0.5V 160-MHz 260uW all digital phase-locked loop. | Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng |
| 2008 | DDECS | A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. | Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw |
| 2007 | ISCAS | A Sub-1V Low-Power High-Speed Static Frequency Divider. | Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su |
| 2006 | DATE | A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. | Kuo-Hsing Cheng, Yu-Lung Lo |
| 2006 | ISCAS | A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. | Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng |
| 2006 | ISCAS | Self-sampled vernier delay line for built-in clock jitter measurement. | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang |
| 2005 | ISCAS | A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang |
| 2005 | ISCAS | A phase-detect synchronous mirror delay for clock skew-compensation circuits. | Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su |
| 2004 | ISCAS | A 14-bit, 200 MS/s digital-to-analog converter without trimming. | Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu |
| 2004 | ISCAS | Static divided word matching line for low-power Content Addressable Memory design. | Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang |
| 2004 | ISCAS | A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. | Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo |
| 2004 | ISCAS | A fast-lock DLL with power-on reset circuit. | Kuo-Hsing Cheng, Yu-Lung Lo |
| 2003 | ISCAS | A CMOS charge pump for sub-2.0 V operation. | Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei |
| 2003 | ISCAS | BIST for clock jitter measurements. | Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen |
| 2003 | ISCAS | A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. | Kuo-Hsing Cheng, Yung-Hsiang Lin |
| 2003 | ISCAS | A new robust handshake for asymmetric asynchronous micro-pipelines. | Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang |
| 2003 | ISCAS | A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. | Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu |
| 2002 | VLSID | Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. | Kuo-Hsing Cheng, Shun-Wen Cheng |
| 2001 | ISCAS | ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. | Shun-Wen Cheng, Kuo-Hsing Cheng |
| 2001 | ISCAS | A low-power high driving ability voltage control oscillator used in PLL. | Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung |
| 2000 | ISCAS | The design and implementation of DCT/IDCT chip with novel architecture. | Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin |
| 1995 | ISCAS | Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. | Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu |
| 1995 | ISCAS | A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. | Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng |
| 1994 | ISCAS | Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. | Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu |