"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).
Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
Browse the full ISLPED paper archive.
Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
Browse the full ISLPED paper archive.